This patch adjusts the top device tree for the CN9132 development board
(variant A), based on the sources which are common for the Cn913x SoCs.
Also an .inf file is added to allow its compilation.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22
++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 ------
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++++++++++++------
3 files changed, 36 insertions(+), 12 deletions(-)
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
new file mode 100644
index 0000000..c9e3b04
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #
gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9132-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
index e9464f8..724d7dc 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
@@ -55,12 +55,6 @@
&cp2_sata0 {
status = "okay";
- /* SLM-1521-V2, CON4 */
- sata-port@0 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy2 0>;
- };
};
/* CON 2 on SLM-1683 - microSD */
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
index 8613607..7dc6c6e 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
@@ -6,15 +6,23 @@
*/
#undef CP110_NUM
-#undef CP110_PCIE_MEM_SIZE
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_BUS_MEM_BASE
+#undef CP110_PCIEx_MEM_BASE
/* CP110-1 Settings */
+#define CP110_NAME cp2
#define CP110_NUM 2
-#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) *
0x1000000)
-#define CP110_PCIEx_BUS_MEM_BASE(iface)
(CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_BASE f6000000
+#define CP110_PCIE0_BASE f6600000
+#define CP110_PCIE1_BASE f6620000
+#define CP110_PCIE2_BASE f6640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
#include "armada-cp110.dtsi"
@@ -124,7 +132,7 @@
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
+ compatible = "marvell,armada-7k-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
--
2.7.4
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