Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG
/ ECAM) on Q35", 2016-03-10) claimed that,On Q35 machine types that QEMU intends to support in the long term, QEMU never lets the RAM below 4 GB exceed 2 GB. Alas, this statement came from a misunderstanding that occurred while we worked out the interface contract. In fact QEMU does allow the 32-bit RAM extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than 2048MB and smaller than 2816MB). In turn, such a RAM size (justifiedly) triggers ASSERT (TopOfLowRam <= PciExBarBase); in MemMapInitialization(), because we placed the 256MB PCIEXBAR at 0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the 32-bit PCI hole would follow the PCIEXBAR, covering the [0x9000_0000, 0xFC00_0000) range.) In order to fix this, reorder the 32-bit PCI hole against the PCIEXBAR, as follows: - start the 32-bit PCI hole where it starts on i440fx as well, that is, at 2GB or TopOfLowRam, whichever is higher; - unlike on i440fx, where the 32-bit PCI hole extends up to 0xFC00_0000, stop it at 0xE000_0000 on q35, - place the PCIEXBAR at 0xE000_0000. (We cannot place the PCIEXBAR at 0xF000_0000 because the 256MB MMIO area that starts there is not entirely free.) Before this patch, the 32-bit PCI hole used to only *end* at the same spot (namely, 0xFC00_0000) between i440fx and q35; now it will only *start* at the same spot (namely, 2GB or TopOfLowRam, whichever is higher) between both boards. On q35, the maximal hole shrinks from 0xFC00_0000 - 0x9000_0000 = 0x6C00_0000 == 1728 MB to 0xE000_0000 - 0x8000_0000 == 1536 MB. We lose 192 MB of the aperture; however, the aperture is now aligned at 1GB, rather than 256 MB, and so it could fit a 1GB BAR even. Regarding the minimal hole (triggered by RAM size 2815MB), its size is 0xE000_0000 - 0xAFF0_0000 = 769 MB which is not great, but probably better than a failed ASSERT. Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Cc: Gerd Hoffmann <kra...@redhat.com> Cc: Jordan Justen <jordan.l.jus...@intel.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <ler...@redhat.com> --- OvmfPkg/OvmfPkgIa32.dsc | 5 +---- OvmfPkg/OvmfPkgIa32X64.dsc | 5 +---- OvmfPkg/OvmfPkgX64.dsc | 5 +---- OvmfPkg/PlatformPei/Platform.c | 9 ++++----- 4 files changed, 7 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 36a0f87258dd..bb55b6fa58e1 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -491,10 +491,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy. It # is only consulted when OVMF runs on Q35. In that case it is programmed into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QEMU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 9b341e17d7ff..06c394a6fb1f 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy. It # is only consulted when OVMF runs on Q35. In that case it is programmed into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QEMU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index a0f87f74dab9..5e0eb043fab9 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy. It # is only consulted when OVMF runs on Q35. In that case it is programmed into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QEMU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 9c013613a1a0..fd8eccaf3e50 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,14 +184,13 @@ MemMapInitialization ( PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. + // The 32-bit PCI host aperture is expected to fall between the top of + // low RAM and the base of the MMCONFIG area. // PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <= PciExBarBase); + ASSERT (PciBase < PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); - PciBase = (UINT32)(PciExBarBase + SIZE_256MB); - PciSize = 0xFC000000 - PciBase; + PciSize = (UINT32)(PciExBarBase - PciBase); } else { PciSize = 0xFC000000 - PciBase; } -- 2.19.1.3.g30247aa5d201 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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