Use CPUID in IA32 implementation of AsmLfence() to verify
that SSE2 is supported before using the LFENCE instruction.
Cc: Liming Gao <liming....@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kin...@intel.com>
---
MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm
b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm
index 44478be35f..0a60ae1d57 100644
--- a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -26,5 +26,17 @@
;------------------------------------------------------------------------------
global ASM_PFX(AsmLfence)
ASM_PFX(AsmLfence):
+ ;
+ ; Use CPUID instruction (CPUID.01H:EDX.SSE2[bit 26] = 1) to test whether
the
+ ; processor supports SSE2 instruction. Save/restore non-volatile register
+ ; EBX that is modified by CPUID
+ ;
+ push ebx
+ mov eax, 1
+ cpuid
+ bt edx, 26
+ jnc Done
lfence
+Done:
+ pop ebx
ret
--
2.21.0.windows.1
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