Hi Tomek, As you can see in the signal wave screenshots, he is using 100Hz, which is already too slow for SPI.
BR, Alan On Wed, Aug 28, 2024 at 12:15 PM Tomek CEDRO <to...@cedro.info> wrote: > are you sure that clock rising/falling edges are configured correctly for > mosi/miso read/write requirements? > > have you tried lowering the frequency to eliminate timing issues? > > -- > CeDeROM, SQ7MHZ, http://www.tomek.cedro.info >
