On 2021-01-22 23:38, Gregory Nutt wrote:
The Raspberry Foundation created their own microcontroller based on
ARM Cortex M0+ with 1MB Flash and 256KB RAM.
I wonder how the performance is with two cores running from QSPI with
no instruction cache?
There is no data cache either. This could be an issue for SMP, at
least if the same RAM banks are being used.
Still I think this could be an interesting SMP platform if there are
no showstopper architectural issues. That could be an interesting
project.
Is there any easy way to get all of the register definition header
files in place (with Apache 2 headers)?
From the datasheet
https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf:
RP2040 is a stateless device, with support for cached
execute-in-place from external QSPI memory.
Figure 2 on page 10 also shows an XIP/Cache between the QSPI and cores.
The datasheet has all (?) register definitions, header files are in the
free SDK in files:
pico-sdk-master\src\rp2040\hardware_regs\include\hardware\regs\*.h
Datasheet has copyright:
Copyright © 2020 Raspberry Pi (Trading) Ltd. The documentation of
the RP2040 microcontroller is licensed under a Creative Commons
Attribution-NoDerivatives 4.0 International (CC BY-ND). Portions
Copyright © 2019 Synopsys, Inc. All rights reserved. Used with
permission. Synopsys & DesignWare are registered trademarks of Synopsys,
Inc. Portions Copyright © 2000-2001, 2005, 2007, 2009, 2011-2012, 2016
ARM Limited. All rights reserved. Used with permission.
build-date: 2021-01-21 build-version: fcd04ef-clean
The headers files have copyright message:
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* SPDX-License-Identifier: BSD-3-Clause
However, I think there is some hidden core info in *.a files without
sources.
Still studying...
Regards,
Arie de Muijnck
