The Raspberry Foundation created their own microcontroller based on ARM Cortex M0+ with 1MB Flash and 256KB RAM.
I wonder how the performance is with two cores running from QSPI with no instruction cache?
There is no data cache either. This could be an issue for SMP, at least if the same RAM banks are being used.
Still I think this could be an interesting SMP platform if there are no showstopper architectural issues. That could be an interesting project.
Is there any easy way to get all of the register definition header files in place (with Apache 2 headers)?
