Hi,
I also debugged on the same board and confirmed that it works, so I will
send a patch.
Booting from barebox with bootm command.
---------------------------------------
RomBOOT
AT91Bootstrap 3.9.1-rc1-00001-g888c3a1 (Sat Dec 21 17:20:28 JST 2019)
MMC: ADMA supported
SD/MMC: Done to load image
>AT91: Detected soc type: sama5d2
AT91: Detected soc subtype: sama5d27cu
Switch to console [cs0]
barebox 2019.12.0-00227-gba23fe8ae-dirty #124 Fri Jan 3 12:06:43 JST 2020
Board: Atmel SAMA5D2 Xplained
AT91: Detected soc type: sama5d2
AT91: Detected soc subtype: sama5d27cu
mdio_bus: miibus0: probed
macb f8008000.ether...@f8008000.of: Cadence GEM at 0xf8008000
atmel-ehci 500000.e...@500000.of: USB EHCI 1.00
atmel_spi f8000000....@f8000000.of: version: 0x311
m25p80 m25p80@00: at25df321a (4096 Kbytes)
sama5d2-sdhci a0000000.sdio-h...@a0000000.of: registered as emmc
emmc: detected MMC card version 4.41
emmc: Capacity: 1872 MiB
emmc: registered emmc
sama5d2-sdhci b0000000.sdio-h...@b0000000.of: registered as sd
sd: detected SD card version 2.0
sd: Capacity: 1910 MiB
sd: registered sd
malloc space: 0x2fdfe640 -> 0x3fdfe63f (size 256 MiB)
envfs: no envfs (magic mismatch) - envfs never written?
Hit any to stop autoboot: 3
barebox:/ bootm /mnt/sd/nuttx
Image Name: nuttx
Created: 2020-02-28 12:07:26 UTC
OS: Linux
Architecture: ARM
Type: Kernel Image
Compression: uncompressed
Data Size: 135040 Bytes = 131.9 KiB
Load Address: 20008000
Entry Point: 20008040
Loading U-Boot uImage '/mnt/sd/nuttx'
commandline: console=ttyS0,115200
NuttShell (NSH) NuttX-8.2
nsh>
---------------------------------------
cheers
Takeyoshi Kikuchi
--
---------------------------------
Takeyoshi Kikuchi
kiku...@centurysys.co.jp
>From 1dcfa58a7dadd89f4ba85fb9b92ace2fbe47d4ee Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Wed, 1 Jan 2020 20:05:33 +0900
Subject: [PATCH 1/6] sama5d2: fix memorymap.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
index a798af70be..36486f22fb 100644
--- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
@@ -133,8 +133,8 @@
# define SAM_TC345_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC channels 3, 4, and 5 */
# define SAM_HSMC_OFFSET 0x00014000 /* 0x00014000-0x00017fff: HSMC */
# define SAM_PDMIC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: HSMC */
-# define SAM_UART0_OFFSET 0x00020000 /* 0x00020000-0x0001ffff: UART0 */
-# define SAM_UART1_OFFSET 0x00022000 /* 0x00022000-0x00023fff: UART1 */
+# define SAM_UART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: UART0 */
+# define SAM_UART1_OFFSET 0x00020000 /* 0x00020000-0x00023fff: UART1 */
# define SAM_UART2_OFFSET 0x00024000 /* 0x00024000-0x00027fff: UART2 */
# define SAM_TWI0_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: TWIHS0 */
# define SAM_PWMC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: PWMC */
@@ -448,7 +448,7 @@
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf00fffff: Internal Peripherals A */
# define SAM_PERIPHB_VSECTION 0xf1000000 /* 0xf1000000-0xf10fffff: Internal Peripherals B */
-# define SAM_PERIPHB_VSECTION 0xf2000000 /* 0xf2000000-0xf20fffff: Internal Peripherals C */
+# define SAM_PERIPHC_VSECTION 0xf2000000 /* 0xf2000000-0xf20fffff: Internal Peripherals C */
#endif
#endif
@@ -460,7 +460,7 @@
#define SAM_MPDDRC_VBASE (SAM_PERIPHA_VSECTION+SAM_MPDDRC_OFFSET)
#define SAM_XDMAC0_VBASE (SAM_PERIPHA_VSECTION+SAM_XDMAC0_OFFSET)
#define SAM_PMC_VBASE (SAM_PERIPHA_VSECTION+SAM_PMC_OFFSET)
-#define SAM_MATRIX0_VBASE (SAM_PERIPHA_VSECTION+SAM_MATRIX0_OFFSET)
+#define SAM_MATRIX64_VBASE (SAM_PERIPHA_VSECTION+SAM_MATRIX0_OFFSET)
#define SAM_AESB_VBASE (SAM_PERIPHA_VSECTION+SAM_AESB_OFFSET)
#define SAM_QSPI0_VBASE (SAM_PERIPHA_VSECTION+SAM_QSPI0_OFFSET)
#define SAM_QSPI1_VBASE (SAM_PERIPHA_VSECTION+SAM_QSPI1_OFFSET)
@@ -511,7 +511,7 @@
#define SAM_UDPHS_VBASE (SAM_PERIPHC_VSECTION+SAM_UDPHS_OFFSET)
#define SAM_ADC_VBASE (SAM_PERIPHC_VSECTION+SAM_ADC_OFFSET)
#define SAM_PIO_VBASE (SAM_PERIPHC_VSECTION+SAM_PIO_OFFSET)
-#define SAM_MATRIX1_VBASE (SAM_PERIPHC_VSECTION+SAM_MATRIX1_OFFSET)
+#define SAM_MATRIX32_VBASE (SAM_PERIPHC_VSECTION+SAM_MATRIX1_OFFSET)
#define SAM_SECUMOD_VBASE (SAM_PERIPHC_VSECTION+SAM_SECUMOD_OFFSET)
#define SAM_TDES_VBASE (SAM_PERIPHC_VSECTION+SAM_TDES_OFFSET)
#define SAM_CLASSD_VBASE (SAM_PERIPHC_VSECTION+SAM_CLASSD_OFFSET)
@@ -861,7 +861,7 @@
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
-# ifdef SAM_ISRAM1_SIZE >= VECTOR_TABLE_SIZE
+# if SAM_ISRAM1_SIZE >= VECTOR_TABLE_SIZE
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# else
--
2.17.1
>From 69a0e36b17bd6e5e16d31c8802b37442ab5e433f Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Wed, 1 Jan 2020 20:06:05 +0900
Subject: [PATCH 2/6] sama5d2: fix SFR AICREDIR_KEY value.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
arch/arm/src/sama5/hardware/sam_sfr.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/src/sama5/hardware/sam_sfr.h b/arch/arm/src/sama5/hardware/sam_sfr.h
index fbd731ec16..26fb5f11c9 100644
--- a/arch/arm/src/sama5/hardware/sam_sfr.h
+++ b/arch/arm/src/sama5/hardware/sam_sfr.h
@@ -279,7 +279,7 @@
# define SFR_AICREDIR_NSAIC (1 << 0) /* Bit 0: Interrupt redirection to Non-Secure AIC */
# define SFR_AICREDIR_ENABLE (1 << 0) /* Bit 0: 1=All interrupts to AIC */
# define SFR_AICREDIR_DISABLE (0) /* Bit 0: 0=Secure interrupts to SAIC */
-# define SFR_AICREDIR_KEY (0x5f67b102) /* Bits 1-31: Access key */
+# define SFR_AICREDIR_KEY (0xb6d81c4d) /* Bits 1-31: Access key */
#endif
--
2.17.1
>From 99eec8ba1389efd76ed0ec73b63d92467ff7c0fe Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Wed, 1 Jan 2020 20:07:11 +0900
Subject: [PATCH 3/6] sama5: set debug register to configure protect mode.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
arch/arm/src/sama5/sam_irq.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c
index 4fb12fc90e..862edddd26 100644
--- a/arch/arm/src/sama5/sam_irq.c
+++ b/arch/arm/src/sama5/sam_irq.c
@@ -392,6 +392,10 @@ static void sam_aic_initialize(uintptr_t base)
putreg32((uint32_t)sam_spurious, base + SAM_AIC_SPU_OFFSET);
+ /* Configure debug register */
+
+ putreg32(AIC_DCR_PROT, base + SAM_AIC_DCR_OFFSET);
+
/* Perform 8 interrupt acknowledgements by writing any value to the
* EOICR register.
*/
--
2.17.1
>From e643638b9459e82d5ce799116e7855bab0fdbbd5 Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Wed, 1 Jan 2020 20:09:04 +0900
Subject: [PATCH 4/6] sama5d2_xult: add 498MHz settings.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
boards/arm/sama5/sama5d2-xult/Kconfig | 3 +
boards/arm/sama5/sama5d2-xult/include/board.h | 9 +
.../sama5/sama5d2-xult/include/board_498mhz.h | 217 ++++++++++++++++++
3 files changed, 229 insertions(+)
create mode 100644 boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
diff --git a/boards/arm/sama5/sama5d2-xult/Kconfig b/boards/arm/sama5/sama5d2-xult/Kconfig
index dad9dc0538..bb486ca026 100644
--- a/boards/arm/sama5/sama5d2-xult/Kconfig
+++ b/boards/arm/sama5/sama5d2-xult/Kconfig
@@ -15,6 +15,9 @@ config SAMA5D2XULT_384MHZ
config SAMA5D2XULT_396MHZ
bool "396 MHz"
+config SAMA5D2XULT_498MHZ
+ bool "498 MHz"
+
config SAMA5D2XULT_528MHZ
bool "528 MHz"
diff --git a/boards/arm/sama5/sama5d2-xult/include/board.h b/boards/arm/sama5/sama5d2-xult/include/board.h
index 0eeb45aa13..7ab198fa35 100644
--- a/boards/arm/sama5/sama5d2-xult/include/board.h
+++ b/boards/arm/sama5/sama5d2-xult/include/board.h
@@ -91,6 +91,15 @@
# include <arch/board/board_384mhz.h>
+#elif defined(CONFIG_SAMA5D2XULT_498MHZ)
+
+/* This is the configuration results in a CPU clock of 498MHz.
+ *
+ * In this configuration, UPLL is the source of the UHPHS clock (if enabled).
+ */
+
+# include <arch/board/board_498mhz.h>
+
#elif defined(CONFIG_SAMA5D2XULT_528MHZ)
/* This is the configuration results in a CPU clock of 528MHz.
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
new file mode 100644
index 0000000000..d86998d62e
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
@@ -0,0 +1,217 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
+ *
+ * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H
+#define __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
+ * These definitions will configure operational clocking.
+ *
+ * This is the configuration results in a CPU clock of 498MHz:
+ *
+ * MAINOSC: Frequency = 12MHz (crystal)
+ * PLLA: PLL Multiplier = 43+1 to generate PLLACK = 498MHz
+ * Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
+ * MCK = 166MHz
+ * CPU clock = 498MHz
+ */
+
+/* Main oscillator register settings.
+ *
+ * The start up time should be should be:
+ * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
+ */
+
+#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
+
+/* PLLA configuration.
+ *
+ * Multipler = 43+1: PLLACK = 44 * 12MHz = 498MHz
+ */
+
+#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
+#define BOARD_CKGR_PLLAR_OUT (0)
+#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
+
+/* PMC master clock register settings.
+ *
+ * Master/Processor Clock Source Selection = PLLA
+ * Master/Processor Clock Prescaler = 1
+ * PLLA Divider = 1
+ * Master Clock Division (MDIV) = 4
+ *
+ * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
+ *
+ * Prescaler input = 498MHz / 1 = 498MHz
+ * Prescaler output = 498MHz / 1 = 498MHz
+ * Processor Clock (PCK) = 498MHz
+ * Master clock (MCK) = 498MHz / 4 = 132MHz
+ */
+
+#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
+#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
+#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1
+#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4
+
+/* ADC Configuration
+ *
+ * ADCClock = MCK / ((PRESCAL+1) * 2)
+ *
+ * Given:
+ * MCK = 132MHz
+ * ADCClock = 8MHz
+ * Then:
+ * PRESCAL = 7.25
+ *
+ * PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz
+ */
+
+#define BOARD_ADC_PRESCAL (7)
+#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
+#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
+
+/* Resulting frequencies */
+
+#define BOARD_MAINCK_FREQUENCY BOARD_MAINOSC_FREQUENCY
+#define BOARD_PLLA_FREQUENCY (996000000) /* PLLACK: 83 * 12Mhz / 1 */
+#define BOARD_PCK_FREQUENCY (498000000) /* CPU: PLLACK / 2 / 1 */
+#define BOARD_MCK_FREQUENCY (166000000) /* MCK: PLLACK / 1 / 1 / 3 */
+#define BOARD_ADCCLK_FREQUENCY (83000000) /* ADCCLK: MCK / ((7+1)*2) */
+
+/* Clocking to certain peripherals may be MCK/2.
+ *
+ * REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
+ */
+
+#define BOARD_PIT_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+#define BOARD_FLEXCOM_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+
+#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
+ defined(CONFIG_SAMA5_UDPHS)
+
+/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
+ * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
+ * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
+ * the 12MHz internal RC oscillator on a an external 12MHz crystal. The
+ * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
+ *
+ * For High-speed operations, the user has to perform the following:
+ *
+ * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
+ * PMC_PCER register.
+ * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
+ * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
+ * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
+ * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
+ * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
+ * register.
+ * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
+ * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
+ * selected.
+ * 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
+ *
+ * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
+ * driver is initialized.
+ */
+
+# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
+# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
+# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
+#endif
+
+/* HSMCI clocking
+ *
+ * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
+ * divided by (2*(CLKDIV) + CLOCKODD + 2).
+ *
+ * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
+ *
+ * Where CLKDIV has a range of 0-255.
+ */
+
+/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */
+
+#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
+
+/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */
+
+#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
+
+/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */
+
+#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
+#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H */
--
2.17.1
>From 3229823973c958b706c06fda18150b13ac07eba6 Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Fri, 3 Jan 2020 15:32:19 +0900
Subject: [PATCH 5/6] sama5: sama5d2x_pio: fix PIO configuration register
value.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
arch/arm/src/sama5/sama5d2x_pio.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c
index 73c82dc91a..fa1ee82dca 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.c
+++ b/arch/arm/src/sama5/sama5d2x_pio.c
@@ -89,9 +89,6 @@ const uintptr_t g_piobase[SAM_NPIO] =
#if SAM_NPIO > 3
, SAM_PIO_IOGROUPD_VBASE
#endif
-#if SAM_NPIO > 4
- , SAM_PIO_IOGROUPE_VBASE
-#endif
};
/* Lookup for non-secure PIOs */
@@ -108,9 +105,6 @@ const uintptr_t g_spiobase[SAM_NPIO] =
#if SAM_NPIO > 3
, SAM_SPIO_IOGROUPD_VBASE
#endif
-#if SAM_NPIO > 4
- , SAM_SPIO_IOGROUPE_VBASE
-#endif
};
/****************************************************************************
@@ -131,9 +125,6 @@ static const char g_portchar[SAM_NPIO] =
#if SAM_NPIO > 3
, 'D'
#endif
-#if SAM_NPIO > 4
- , 'E'
-#endif
};
#endif
@@ -388,7 +379,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
*/
regval = sam_configcommon(cfgset);
- periph = ((cfgset & PIO_CFGR_FUNC_MASK) - PIO_CFGR_FUNC_PERIPHA) >> PIO_CFGR_FUNC_SHIFT;
+ periph = ((cfgset & PIO_MODE_MASK) - PIO_ANALOG) >> PIO_MODE_SHIFT;
regval |= PIO_CFGR_FUNC_PERIPH(periph);
/* Clear some output only bits. Mostly this just simplifies debug. */
@@ -463,15 +454,16 @@ int sam_configpio(pio_pinset_t cfgset)
/* Select the secure or un-secured PIO operation */
+#if 0
if (sam_issecure(cfgset))
{
putreg32(pin, base + SAM_SPIO_SIOSR_OFFSET);
}
else
+#endif
{
putreg32(pin, base + SAM_SPIO_SIONR_OFFSET);
}
-
/* Set the mask register to modify only the specific pin being configured. */
putreg32(pin, base + SAM_PIO_MSKR_OFFSET);
--
2.17.1
>From 3f0b0b6bf6402450b9ef5afb41305538568b0594 Mon Sep 17 00:00:00 2001
From: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
Date: Fri, 28 Feb 2020 21:09:33 +0900
Subject: [PATCH 6/6] sama5d2-xult: nsh: update defconfig.
Signed-off-by: Takeyoshi Kikuchi <kiku...@centurysys.co.jp>
---
boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig b/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig
index f78ff3382e..940a3da207 100644
--- a/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig
+++ b/boards/arm/sama5/sama5d2-xult/configs/nsh/defconfig
@@ -34,7 +34,6 @@ CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_HIDKBD_POLLUSEC=80000
-CONFIG_HOST_WINDOWS=y
CONFIG_I2S=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=16
@@ -56,9 +55,8 @@ CONFIG_RAMLOG_SYSLOG=y
CONFIG_RAM_SIZE=268435456
CONFIG_RAM_START=0x20000000
CONFIG_RAM_VSTART=0x20000000
-CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
-CONFIG_SAMA5D2XULT_528MHZ=y
+CONFIG_SAMA5D2XULT_498MHZ=y
CONFIG_SAMA5_BOOT_SDRAM=y
CONFIG_SAMA5_DDRCS_HEAP_END=0x2fa00000
CONFIG_SAMA5_DDRCS_RESERVE=y
@@ -77,6 +75,9 @@ CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
CONFIG_SYSTEM_NXPLAYER=y
CONFIG_UART1_SERIAL_CONSOLE=y
+CONFIG_UBOOT_UIMAGE=y
+CONFIG_UIMAGE_ENTRY_POINT=0x20008040
+CONFIG_UIMAGE_LOAD_ADDRESS=0x20008000
CONFIG_USBHOST_HIDKBD=y
CONFIG_USBHOST_MSC=y
CONFIG_USER_ENTRYPOINT="nsh_main"
--
2.17.1
