Signed-off-by: Ravi Kumar <ravi1.ku...@amd.com> --- drivers/net/axgbe/axgbe_common.h | 49 +++--- drivers/net/axgbe/axgbe_ethdev.c | 10 +- drivers/net/axgbe/axgbe_ethdev.h | 8 +- drivers/net/axgbe/axgbe_rxtx.c | 12 +- drivers/net/axgbe/axgbe_rxtx.h | 4 +- drivers/net/axgbe/axgbe_rxtx.h.orig | 307 ++++++++++++++++++++++++++++++++++++ 6 files changed, 354 insertions(+), 36 deletions(-) create mode 100644 drivers/net/axgbe/axgbe_rxtx.h.orig
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 9a5808d..0ceeefa 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1506,7 +1506,7 @@ do { \ * register definitions formed using the input names */ #define AXGMAC_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + (_reg))) + rte_read32((void *)((uint8_t *)((_pdata)->xgmac_regs) + (_reg))) #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \ @@ -1514,7 +1514,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg))) + rte_write32((_val), \ + (void *)((uint8_t *)((_pdata)->xgmac_regs) + (_reg))) #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1530,7 +1531,7 @@ do { \ * base register value is calculated by the queue or traffic class number */ #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + \ + rte_read32((void *)((uint8_t *)((_pdata)->xgmac_regs) + \ MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ @@ -1539,7 +1540,7 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + \ + rte_write32((_val), (void *)((uint8_t *)((_pdata)->xgmac_regs) +\ MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ @@ -1556,7 +1557,7 @@ do { \ * base register value is obtained from the ring */ #define AXGMAC_DMA_IOREAD(_channel, _reg) \ - rte_read32((void *)((_channel)->dma_regs + (_reg))) + rte_read32((void *)((uint8_t *)((_channel)->dma_regs) + (_reg))) #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \ @@ -1564,7 +1565,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \ - rte_write32((_val), (void *)((_channel)->dma_regs + (_reg))) + rte_write32((_val), \ + (void *)((uint8_t *)((_channel)->dma_regs) + (_reg))) #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ do { \ @@ -1589,16 +1591,18 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XPCS32_IOWRITE(_pdata, _off, _val) \ - rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write32(_val, \ + (void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off))) #define XPCS32_IOREAD(_pdata, _off) \ - rte_read32((void *)((_pdata)->xpcs_regs + (_off))) + rte_read32((void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off))) #define XPCS16_IOWRITE(_pdata, _off, _val) \ - rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write16(_val, \ + (void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off))) #define XPCS16_IOREAD(_pdata, _off) \ - rte_read16((void *)((_pdata)->xpcs_regs + (_off))) + rte_read16((void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off))) /* Macros for building, reading or writing register values or bits * within the register values of SerDes integration registers. @@ -1614,7 +1618,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XSIR0_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir0_regs + (_reg))) + rte_read16((void *)((uint8_t *)((_pdata)->sir0_regs) + (_reg))) #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ @@ -1622,7 +1626,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR0_IOWRITE(_pdata, _reg, _val) \ - rte_read16((_val), (void *)((_pdata)->sir0_regs + (_reg))) + rte_read16((_val), \ + (void *)((uint8_t *)((_pdata)->sir0_regs) + (_reg))) #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1634,7 +1639,7 @@ do { \ } while (0) #define XSIR1_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir1_regs + _reg)) + rte_read16((void *)((uint8_t *)((_pdata)->sir1_regs) + _reg)) #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ @@ -1642,7 +1647,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR1_IOWRITE(_pdata, _reg, _val) \ - rte_read16((_val), (void *)((_pdata)->sir1_regs + (_reg))) + rte_read16((_val), \ + (void *)((uint8_t *)((_pdata)->sir1_regs) + (_reg))) #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1657,7 +1663,7 @@ do { \ * within the register values of SerDes RxTx registers. */ #define XRXTX_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->rxtx_regs + (_reg))) + rte_read16((void *)((uint8_t *)((_pdata)->rxtx_regs) + (_reg))) #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ @@ -1665,7 +1671,8 @@ do { \ _reg##_##_field##_WIDTH) #define XRXTX_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg))) + rte_write16((_val), \ + (void *)((uint8_t *)((_pdata)->rxtx_regs) + (_reg))) #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1690,7 +1697,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XP_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xprop_regs + (_reg))) + rte_read32((void *)((uint8_t *)((_pdata)->xprop_regs) + (_reg))) #define XP_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XP_IOREAD((_pdata), (_reg)), \ @@ -1698,7 +1705,8 @@ do { \ _reg##_##_field##_WIDTH) #define XP_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg))) + rte_write32((_val), \ + (void *)((uint8_t *)((_pdata)->xprop_regs) + (_reg))) #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1723,7 +1731,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XI2C_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xi2c_regs + (_reg))) + rte_read32((void *)((uint8_t *)((_pdata)->xi2c_regs) + (_reg))) #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ @@ -1731,7 +1739,8 @@ do { \ _reg##_##_field##_WIDTH) #define XI2C_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg))) + rte_write32((_val), \ + (void *)((uint8_t *)((_pdata)->xi2c_regs) + (_reg))) #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index 84adf96..fca5a2a 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -710,10 +710,12 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) rte_eth_copy_pci_info(eth_dev, pci_dev); pdata->xgmac_regs = - (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; - pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET; - pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET; - pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; + (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; + pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs + + AXGBE_MAC_PROP_OFFSET); + pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs + + AXGBE_I2C_CTRL_OFFSET); + pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; /* version specific driver data*/ if (pci_dev->id.device_id == 0x1458) diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index a36a341..a4fa94f 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -567,10 +567,10 @@ struct axgbe_port { struct axgbe_version_data *vdata; /* AXGMAC/XPCS related mmio registers */ - uint64_t xgmac_regs; /* AXGMAC CSRs */ - uint64_t xpcs_regs; /* XPCS MMD registers */ - uint64_t xprop_regs; /* AXGBE property registers */ - uint64_t xi2c_regs; /* AXGBE I2C CSRs */ + void *xgmac_regs; /* AXGMAC CSRs */ + void *xpcs_regs; /* XPCS MMD registers */ + void *xprop_regs; /* AXGBE property registers */ + void *xi2c_regs; /* AXGBE I2C CSRs */ /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index 3e92f84..7981cdd 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -192,9 +192,9 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, rxq->queue_id = queue_idx; rxq->port_id = dev->data->port_id; rxq->nb_desc = rx_desc; - rxq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + - (DMA_CH_INC * rxq->queue_id); - rxq->dma_tail_reg = (volatile uint32_t *)(rxq->dma_regs + + rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + + (DMA_CH_INC * rxq->queue_id)); + rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs + DMA_CH_RDTR_LO); rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 : @@ -509,9 +509,9 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, txq->desc = tz->addr; txq->queue_id = queue_idx; txq->port_id = dev->data->port_id; - txq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + - (DMA_CH_INC * txq->queue_id); - txq->dma_tail_reg = (volatile uint32_t *)(txq->dma_regs + + txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + + (DMA_CH_INC * txq->queue_id)); + txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs + DMA_CH_TDTR_LO); txq->cur = 0; txq->dirty = 0; diff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h index 6cac673..8bf774c 100644 --- a/drivers/net/axgbe/axgbe_rxtx.h +++ b/drivers/net/axgbe/axgbe_rxtx.h @@ -201,7 +201,7 @@ struct axgbe_rx_queue { /* Ring physical address */ uint64_t ring_phys_addr; /* Dma Channel register address */ - uint64_t dma_regs; + void *dma_regs; /* Dma channel tail register address*/ volatile uint32_t *dma_tail_reg; /* DPDK queue index */ @@ -248,7 +248,7 @@ struct axgbe_tx_queue { /* Physical address of ring */ uint64_t ring_phys_addr; /* Dma channel register space */ - uint64_t dma_regs; + void *dma_regs; /* Dma tail register address of ring*/ volatile uint32_t *dma_tail_reg; /* Tx queue index/id*/ diff --git a/drivers/net/axgbe/axgbe_rxtx.h.orig b/drivers/net/axgbe/axgbe_rxtx.h.orig new file mode 100644 index 0000000..6cac673 --- /dev/null +++ b/drivers/net/axgbe/axgbe_rxtx.h.orig @@ -0,0 +1,307 @@ +/*- + * Copyright(c) 2017 Advanced Micro Devices, Inc. + * All rights reserved. + * + * AMD 10Gb Ethernet driver + * + * This file is available to you under your choice of the following two + * licenses: + * + * License 1: GPLv2 + * + * Copyright (c) 2017 Advanced Micro Devices, Inc. + * + * This file is free software; you may copy, redistribute and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * This file incorporates work covered by the following copyright and + * permission notice: + * + * Copyright (c) 2013 Synopsys, Inc. + * + * The Synopsys DWC ETHER XGMAC Software Driver and documentation + * (hereinafter "Software") is an unsupported proprietary work of Synopsys, + * Inc. unless otherwise expressly agreed to in writing between Synopsys + * and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product + * under any End User Software License Agreement or Agreement for Licensed + * Product with Synopsys or any supplement thereto. Permission is hereby + * granted, free of charge, to any person obtaining a copy of this software + * annotated with this license and the Software, to deal in the Software + * without restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * License 2: Modified BSD + * + * Copyright (c) 2017 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * <COPYRIGHT HOLDER> BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file incorporates work covered by the following copyright and + * permission notice: + * + * Copyright (c) 2013 Synopsys, Inc. + * + * The Synopsys DWC ETHER XGMAC Software Driver and documentation + * (hereinafter "Software") is an unsupported proprietary work of Synopsys, + * Inc. unless otherwise expressly agreed to in writing between Synopsys + * and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product + * under any End User Software License Agreement or Agreement for Licensed + * Product with Synopsys or any supplement thereto. Permission is hereby + * granted, free of charge, to any person obtaining a copy of this software + * annotated with this license and the Software, to deal in the Software + * without restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AXGBE_RXTX_H_ +#define _AXGBE_RXTX_H_ + +/* to suppress gcc warnings related to descriptor casting */ +#ifdef RTE_TOOLCHAIN_GCC +#pragma GCC diagnostic ignored "-Wcast-qual" +#endif +#ifdef RTE_TOOLCHAIN_CLANG +#pragma GCC diagnostic ignored "-Wcast-qual" +#endif + +/* Descriptor related defines */ +#define AXGBE_MAX_RING_DESC 4096 /*should be power of 2*/ +#define AXGBE_TX_DESC_MIN_FREE (AXGBE_MAX_RING_DESC >> 3) +#define AXGBE_TX_DESC_MAX_PROC (AXGBE_MAX_RING_DESC >> 1) +#define AXGBE_MIN_RING_DESC 32 +#define RTE_AXGBE_DESCS_PER_LOOP 4 +#define RTE_AXGBE_MAX_RX_BURST 32 + +#define AXGBE_RX_FREE_THRESH 32 +#define AXGBE_TX_FREE_THRESH 32 + +#define AXGBE_DESC_ALIGN 128 +#define AXGBE_DESC_OWN 0x80000000 +#define AXGBE_ERR_STATUS 0x000f0000 +#define AXGBE_L3_CSUM_ERR 0x00050000 +#define AXGBE_L4_CSUM_ERR 0x00060000 + +#include "axgbe_common.h" + +#define AXGBE_GET_DESC_PT(_queue, _idx) \ + (((_queue)->desc) + \ + ((_idx) & ((_queue)->nb_desc - 1))) + +#define AXGBE_GET_DESC_IDX(_queue, _idx) \ + ((_idx) & ((_queue)->nb_desc - 1)) \ + +/* Rx desc format */ +union axgbe_rx_desc { + struct { + uint64_t baddr; + uint32_t desc2; + uint32_t desc3; + } read; + struct { + uint32_t desc0; + uint32_t desc1; + uint32_t desc2; + uint32_t desc3; + } write; +}; + +struct axgbe_rx_queue { + /* membuf pool for rx buffers */ + struct rte_mempool *mb_pool; + /* H/w Rx buffer size configured in DMA */ + unsigned int buf_size; + /* CRC h/w offload */ + uint16_t crc_len; + /* address of s/w rx buffers */ + struct rte_mbuf **sw_ring; + /* Port private data */ + struct axgbe_port *pdata; + /* Number of Rx descriptors in queue */ + uint16_t nb_desc; + /* max free RX desc to hold */ + uint16_t free_thresh; + /* Index of descriptor to check for packet availability */ + uint64_t cur; + /* Index of descriptor to check for buffer reallocation */ + uint64_t dirty; + /* Software Rx descriptor ring*/ + volatile union axgbe_rx_desc *desc; + /* Ring physical address */ + uint64_t ring_phys_addr; + /* Dma Channel register address */ + uint64_t dma_regs; + /* Dma channel tail register address*/ + volatile uint32_t *dma_tail_reg; + /* DPDK queue index */ + uint16_t queue_id; + /* dpdk port id*/ + uint16_t port_id; + /* queue stats */ + uint64_t pkts; + uint64_t bytes; + uint64_t errors; + /* Number of mbufs allocated from pool*/ + uint64_t mbuf_alloc; + +} ____cacheline_aligned; + +/*Tx descriptor format */ +struct axgbe_tx_desc { + phys_addr_t baddr; + uint32_t desc2; + uint32_t desc3; +}; + +struct axgbe_tx_queue { + /* Port private data reference */ + struct axgbe_port *pdata; + /* Number of Tx descriptors in queue*/ + uint16_t nb_desc; + /* Start freeing TX buffers if there are less free descriptors than + * this value + */ + uint16_t free_thresh; + /* Available descriptors for Tx processing*/ + uint16_t nb_desc_free; + /* Batch of mbufs/descs to release */ + uint16_t free_batch_cnt; + /* Flag for vector support */ + uint16_t vector_disable; + /* Index of descriptor to be used for current transfer */ + uint64_t cur; + /* Index of descriptor to check for transfer complete */ + uint64_t dirty; + /* Virtual address of ring */ + volatile struct axgbe_tx_desc *desc; + /* Physical address of ring */ + uint64_t ring_phys_addr; + /* Dma channel register space */ + uint64_t dma_regs; + /* Dma tail register address of ring*/ + volatile uint32_t *dma_tail_reg; + /* Tx queue index/id*/ + uint16_t queue_id; + /* Reference to hold Tx mbufs mapped to Tx descriptors freed + * after transmission confirmation + */ + struct rte_mbuf **sw_ring; + /* dpdk port id*/ + uint16_t port_id; + /* queue stats */ + uint64_t pkts; + uint64_t bytes; + uint64_t errors; + +} __rte_cache_aligned; + +/*Queue related APIs */ + +/* + * RX/TX function prototypes + */ + + +void axgbe_dev_tx_queue_release(void *txq); +int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); +void axgbe_dev_enable_tx(struct rte_eth_dev *dev); +void axgbe_dev_disable_tx(struct rte_eth_dev *dev); +int axgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int axgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); + +uint16_t axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); +uint16_t axgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); + + +void axgbe_dev_rx_queue_release(void *rxq); +int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool); +void axgbe_dev_enable_rx(struct rte_eth_dev *dev); +void axgbe_dev_disable_rx(struct rte_eth_dev *dev); +int axgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int axgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); +uint16_t axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); +uint16_t axgbe_recv_pkts_threshold_refresh(void *rx_queue, + struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); +void axgbe_dev_clear_queues(struct rte_eth_dev *dev); + +#endif /* _AXGBE_RXTX_H_ */ -- 2.7.4