On Thu, Oct 05, 2017 at 04:00:30PM -0700, Yongseok Koh wrote: > The size of Rx completion entry should match the size of a cacheline. This > is already reflected in struct mlx5_cqe by adding 64bytes padding if a > cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline. > > Signed-off-by: Yongseok Koh <ys...@mellanox.com> Acked-by: Nelio Laranjeiro <nelio.laranje...@6wind.com>
-- Nélio Laranjeiro 6WIND
