28/04/2017 04:14, Jianbo Liu: > On 27 April 2017 at 00:29, Jerin Jacob <jerin.ja...@caviumnetworks.com> wrote: > > armv8 implementations may have 64B or 128B cache line. > > Setting to the maximum available cache line size in generic config to > > address minimum DMA alignment across all arm64 implementations. > > > > Increasing the cacheline size has no negative impact to cache invalidation > > on systems with a smaller cache line. > > > > The need for the minimum DMA alignment has impact on functional aspects > > of the platform so default config should cater the functional aspects. > > > > There is an impact on memory usage with this scheme, but that's not too > > important for the single image arm64 distribution use case. > > > > The arm64 linux kernel followed the similar approach for single > > arm64 image use case. > > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h > > > > Signed-off-by: Jerin Jacob <jerin.ja...@caviumnetworks.com> > > Acked-by: Jianbo Liu <jianbo....@linaro.org>
Applied, thanks
