Add a L3/L4 filtering definition of register MRQC for
the future use.
Signed-off-by: Wenzhuo Lu <wenzhuo...@intel.com>
---
drivers/net/ixgbe/base/ixgbe_type.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
b/drivers/net/ixgbe/base/ixgbe_type.h
index bb1f85b..6acd966 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -2622,6 +2622,7 @@ enum {
#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
+#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */
#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
--
1.9.3
