On 27 December 2016 at 17:49, Jerin Jacob
<jerin.ja...@caviumnetworks.com> wrote:
> dsb instruction based barrier is used for non smp
> version of memory barrier.
>
> Fixes: d708f01b7102 ("eal/arm: add atomic operations for ARMv8")
>
> CC: Jianbo Liu <jianbo....@linaro.org>
> CC: sta...@dpdk.org
> Signed-off-by: Jerin Jacob <jerin.ja...@caviumnetworks.com>
> ---
> lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index d854aac..bc7de64 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -43,7 +43,8 @@ extern "C" {
>
> #include "generic/rte_atomic.h"
>
> -#define dmb(opt) do { asm volatile("dmb " #opt : : : "memory"); } while (0)
> +#define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
> +#define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
>
> /**
> * General memory barrier.
> @@ -54,7 +55,7 @@ extern "C" {
> */
> static inline void rte_mb(void)
> {
> - dmb(ish);
> + dsb(sy);
> }
>
> /**
> @@ -66,7 +67,7 @@ static inline void rte_mb(void)
> */
> static inline void rte_wmb(void)
> {
> - dmb(ishst);
> + dsb(st);
> }
>
> /**
> @@ -78,7 +79,7 @@ static inline void rte_wmb(void)
> */
> static inline void rte_rmb(void)
> {
> - dmb(ishld);
> + dsb(ld);
> }
>
> #define rte_smp_mb() rte_mb()
> --
> 2.5.5
>
Acked-by: Jianbo Liu <jianbo....@linaro.org>
