Hello Olivier, On Fri, May 13, 2016 at 2:50 PM, Olivier Matz <olivier.matz at 6wind.com> wrote: > From: David Marchand <david.marchand at 6wind.com> > > Although ppc supports both endianesses, qemu supposes that the cpu is > big endian and enforces this for the virtio-net stuff. > > Fix PCI accesses in legacy mode. Only ppc64le is supported at the moment. > > Signed-off-by: David Marchand <david.marchand at 6wind.com> > Signed-off-by: Olivier Matz <olivier.matz at 6wind.com> > --- > drivers/net/virtio/virtio_pci.c | 44 > +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c > index 9cdca06..bdb89fd 100644 > --- a/drivers/net/virtio/virtio_pci.c > +++ b/drivers/net/virtio/virtio_pci.c > @@ -55,18 +55,62 @@ > */ > #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20) > > +/* > + * Since we are in legacy mode: > + * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf > + * > + * "Note that this is possible because while the virtio header is PCI (i.e. > + * little) endian, the device-specific region is encoded in the native > endian of > + * the guest (where such distinction is applicable)." > + * > + * For powerpc which supports both, qemu supposes that cpu is big endian and > + * enforces this for the virtio-net stuff. > + */ > + > static void > legacy_read_dev_config(struct virtio_hw *hw, size_t offset, > void *dst, int length) > { > rte_eal_pci_ioport_read(&hw->io, dst, length, > VIRTIO_PCI_CONFIG(hw) + offset); > +#ifdef RTE_ARCH_PPC_64 > + switch (length) { > + case 4: > + *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst); > + break; > + case 2: > + *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst); > + break; > + default: > + break; > + } > +#endif > }
I think that, in the original patch, I was handling lengths different than 1, 2 and 4 ;-) Idem for write. -- David Marchand
