On Wed, Jan 06, 2016 at 11:47:28AM +0000, Andralojc, WojciechX wrote: > > From: Andralojc, WojciechX > > Sent: Thursday, December 17, 2015 12:13 PM > > To: dev at dpdk.org > > Cc: Andralojc, WojciechX > > Subject: [PATCH] Patch introducing API to read/write Intel Architecture > > Model > > Specific Registers (MSR), rte_msr_read and rte_msr_write functions. > > > > There is work in progress to implement Intel Cache Allocation Technology > > (CAT) > > support in DPDK, this technology is programmed through MSRs. > > In the future it will be possible to program CAT through Linux cgroups and > > DPDK > > CAT implementation will take advantage of it. > > > > MSR R/W's are privileged ring 0 operations and they must be done in kernel > > space. For this reason implementation utilizes Linux MSR driver. > > > > Signed-off-by: Wojciech Andralojc <wojciechx.andralojc at intel.com> > > I've got suggestion offline that as MSRs are IA specific, > I should not give the dummy APIs for the other arches > and move MSR access functions into the EAL specific APIs > or some place more arch specific. > Do you find submitted MSR patch OK? > or do you agree with the above feedback and patch should be re-worked?
+1 IMO, No need to expose this function as EAL as other archs can't implement this.I think, a IA specific function under lib/librte_eal/common/include/arch/x86/ and removing rte_* from internal architecture functions looks more appropriate Jerin > I am looking forward to your feedback > > Thank you! > > Wojciech Andralojc > -------------------------------------------------------------- > Intel Research and Development Ireland Limited > Registered in Ireland > Registered Office: Collinstown Industrial Park, Leixlip, County Kildare > Registered Number: 308263 > > > This e-mail and any attachments may contain confidential material for the sole > use of the intended recipient(s). Any review or distribution by others is > strictly prohibited. If you are not the intended recipient, please contact the > sender and delete all copies. >
