On Tue, Jun 30, 2026 at 08:06:51AM -0400, Dawid Wesierski wrote: > From: Marek Kasiewicz <[email protected]> > > The Intel E810 hardware supports up to 8160 (8K - 32) descriptors per > TX/RX ring, but IAVF_MAX_RING_DESC caps it at 4096. Applications that > need deep descriptor rings for hardware rate-limited pacing (e.g., > ST2110 video with thousands of packets per frame) cannot queue enough > packets before the pacing epoch begins. > > Increase IAVF_MAX_RING_DESC to the hardware maximum of 8160 to allow > full utilization of the ring depth on E810 VFs. > > Signed-off-by: Marek Kasiewicz <[email protected]> > Signed-off-by: Dawid Wesierski <[email protected]>
Acked-by: Bruce Richardson <[email protected]> > --- > .mailmap | 2 ++ > drivers/net/intel/iavf/iavf_rxtx.h | 2 +- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/.mailmap b/.mailmap > index 4001e5fb0e..d7b175de2a 100644 > --- a/.mailmap > +++ b/.mailmap > @@ -366,6 +366,7 @@ David Zeng <[email protected]> > Davide Caratti <[email protected]> > Dawid Gorecki <[email protected]> > Dawid Jurczak <[email protected]> > +Dawid Wesierski <[email protected]> > Dawid Zielinski <[email protected]> > Dawid Łukwiński <[email protected]> > Daxue Gao <[email protected]> > @@ -1014,6 +1015,7 @@ Marcin Wilk <[email protected]> > Marcin Wojtas <[email protected]> > Marcin Zapolski <[email protected]> > Marco Varlese <[email protected]> > +Marek Kasiewicz <[email protected]> > Marek Mical <[email protected]> > Marek Zalfresso-jundzillo <[email protected]> > Maria Lingemark <[email protected]> > diff --git a/drivers/net/intel/iavf/iavf_rxtx.h > b/drivers/net/intel/iavf/iavf_rxtx.h > index 8449236d4d..22ea415f44 100644 > --- a/drivers/net/intel/iavf/iavf_rxtx.h > +++ b/drivers/net/intel/iavf/iavf_rxtx.h > @@ -16,7 +16,7 @@ > /* In QLEN must be whole number of 32 descriptors. */ > #define IAVF_ALIGN_RING_DESC 32 > #define IAVF_MIN_RING_DESC 64 > -#define IAVF_MAX_RING_DESC 4096 > +#define IAVF_MAX_RING_DESC (8192 - 32) > #define IAVF_DMA_MEM_ALIGN 4096 > /* Base address of the HW descriptor ring should be 128B aligned. */ > #define IAVF_RING_BASE_ALIGN 128 > -- > 2.47.3 > > --------------------------------------------------------------------- > Intel Technology Poland sp. z o.o. > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > 957-07-52-316 | Kapital zakladowy 200.000 PLN. > Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy > z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w > transakcjach handlowych. > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i > moze zawierac informacje poufne. W razie przypadkowego otrzymania tej > wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; > jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). If you are not the intended recipient, > please contact the sender and delete all copies; any review or distribution > by others is strictly prohibited.
