From: Kalesh AP <[email protected]> If firmware advertises support for the TX timestamp completion and PTP is also supported, then enable this feature when allocating TX rings.
The new BCM5760X chips will return the timestamp of TX packets in a new completion. Add logic to handle this completion type to retrieve the timestamp. Logic to retrieve Rx timestamp is same as Thor. Signed-off-by: Kalesh AP <[email protected]> Signed-off-by: Mohammad Shuab Siddique <[email protected]> --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_ethdev.c | 8 +++++--- drivers/net/bnxt/bnxt_hwrm.c | 8 +++++++- drivers/net/bnxt/bnxt_rxr.c | 10 +++++----- drivers/net/bnxt/bnxt_txr.c | 16 ++++++++++++++++ 5 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 7515f0564f..03df28e64a 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -410,6 +410,8 @@ struct bnxt_ptp_cfg { uint64_t current_time; uint64_t old_time; rte_spinlock_t ptp_lock; + /* On P7, the Tx timestamp is present in the Tx completion record */ + uint64_t tx_timestamp; }; struct bnxt_coal { @@ -892,6 +894,7 @@ struct bnxt { (bp)->hwrm_spec_code >= HWRM_VERSION_1_9_2 && \ !BNXT_VF((bp))) #define BNXT_FW_CAP_UDP_GSO BIT(13) +#define BNXT_FW_CAP_TX_TS_CMP BIT(16) #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\ (bp)->app_id != 0xFF) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 64b12ada9f..72a31dfbb5 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -3889,9 +3889,11 @@ bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, if (!ptp) return -ENOTSUP; - /* TODO Revisit for Thor 2 */ - rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, - &tx_tstamp_cycles); + if (BNXT_CHIP_P7(bp)) + tx_tstamp_cycles = ptp->tx_timestamp; + else + rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, + &tx_tstamp_cycles); ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); *timestamp = rte_ns_to_timespec(ns); diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 68e75e43bd..e4ae27d3f4 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -1027,7 +1027,8 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp) HWRM_CHECK_RESULT(); - if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS)) + if (!BNXT_CHIP_P7(bp) && + !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS)) return 0; if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS) @@ -1224,6 +1225,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS; if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED) bp->fw_cap |= BNXT_FW_CAP_UDP_GSO; + if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED) + bp->fw_cap |= BNXT_FW_CAP_TX_TS_CMP; if (flags_ext3 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED) bp->fw_cap |= BNXT_FW_CAP_RX_RATE_PROFILE; @@ -2192,6 +2195,9 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp, if (stats_ctx_id != INVALID_STATS_CTX_ID) enables |= HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID; + if (bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP && bp->ptp_cfg) + req.flags = + rte_cpu_to_le_16(HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE); break; case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX: req.ring_type = ring_type; diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index fb7c70fd45..293b5c03b6 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -740,13 +740,13 @@ static void bnxt_get_rx_ts(struct bnxt *bp) } static void -bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl) +bnxt_get_rx_ts_p5_p7(struct bnxt *bp, uint32_t rx_ts_cmpl) { struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; - uint64_t last_hwrm_time = 0; + uint64_t last_hwrm_time; uint64_t pkt_time = 0; - if (!BNXT_CHIP_P5(bp) || !ptp) + if (!ptp) return; /* On P5, Rx timestamps are provided directly in the @@ -1210,8 +1210,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt, bp->ptp_cfg) { mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | RTE_MBUF_F_RX_IEEE1588_TMST; - if (BNXT_CHIP_P5(bp)) - bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder); + if (BNXT_CHIP_P5_P7(bp)) + bnxt_get_rx_ts_p5_p7(rxq->bp, rxcmp1->reorder); else bnxt_get_rx_ts(rxq->bp); #ifndef RTE_IOVA_IN_MBUF diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c index 7ef5b15ae8..fb5be224d9 100644 --- a/drivers/net/bnxt/bnxt_txr.c +++ b/drivers/net/bnxt/bnxt_txr.c @@ -600,6 +600,20 @@ static bool bnxt_is_tx_cmpl_type(uint16_t type) type == CMPL_BASE_TYPE_TX_L2); } +static void bnxt_get_tx_ts_p7(struct bnxt *bp, struct tx_cmpl_packet_timestamp *txcmp) +{ + uint64_t tx_timestamp; + + if (!(bp->fw_cap & BNXT_FW_CAP_TX_TS_CMP)) + return; + + if (!bp->ptp_cfg || !bp->ieee_1588) + return; + + tx_timestamp = rte_le_to_cpu_16(txcmp->ts_ns_mid); + bp->ptp_cfg->tx_timestamp = (tx_timestamp << 32) | rte_le_to_cpu_32(txcmp->ts_ns_lo); +} + static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq) { uint32_t nb_tx_pkts = 0, cons, ring_mask, opaque; @@ -629,6 +643,8 @@ static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq) RTE_LOG_DP_LINE(ERR, BNXT, "Unhandled CMP type %02x", CMP_TYPE(txcmp)); + if (CMP_TYPE(txcmp) == CMPL_BASE_TYPE_TX_L2_PKT_TS) + bnxt_get_tx_ts_p7(txq->bp, (struct tx_cmpl_packet_timestamp *)txcmp); raw_cons = NEXT_RAW_CMP(raw_cons); } while (nb_tx_pkts < ring_mask); -- 2.47.3
