Provide link type along with link status get. Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com> --- drivers/net/cnxk/cnxk_ethdev.c | 21 ++++++++++++++++++++- drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_link.c | 10 +++++++--- 3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 4dba4968d5..9dc442fa6d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -6,7 +6,7 @@ #include <rte_eventdev.h> #include <rte_pmd_cnxk.h> -const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { +static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, @@ -60,6 +60,17 @@ const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, }; +static const uint8_t cnxk_port_type[] = { + [CGX_PORT_TP] = RTE_ETH_LINK_TYPE_TP, + [CGX_PORT_AUI] = RTE_ETH_LINK_TYPE_AUI, + [CGX_PORT_MII] = RTE_ETH_LINK_TYPE_MII, + [CGX_PORT_FIBRE] = RTE_ETH_LINK_TYPE_FIBRE, + [CGX_PORT_BNC] = RTE_ETH_LINK_TYPE_BNC, + [CGX_PORT_DA] = RTE_ETH_LINK_TYPE_DA, + [CGX_PORT_NONE] = RTE_ETH_LINK_TYPE_NONE, + [CGX_PORT_OTHER] = RTE_ETH_LINK_TYPE_OTHER, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -95,6 +106,7 @@ static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { struct roc_nix_mac_fwdata fwdata; + struct rte_eth_link link; uint32_t speed_capa; uint8_t mode; int rc; @@ -114,6 +126,12 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) if (fwdata.supported_link_modes & BIT_ULL(mode)) speed_capa |= cnxk_mac_modes[mode]; } + dev->link_type = cnxk_port_type[(uint8_t)fwdata.port_type]; + + /* Set link type at init */ + memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; + rte_eth_linkstatus_set(dev->eth_dev, &link); } return speed_capa; @@ -1757,6 +1775,7 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) /* Bring down link status internally */ memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; rte_eth_linkstatus_set(eth_dev, &link); return 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index daf80be51b..5f8df43d42 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -370,6 +370,7 @@ struct cnxk_eth_dev { uint64_t rx_offload_capa; uint64_t tx_offload_capa; uint32_t speed_capa; + uint8_t link_type; /* Configured Rx and Tx offloads */ uint64_t rx_offloads; uint64_t tx_offloads; diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index 903b44de2c..38970eddd6 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -47,14 +47,16 @@ static void nix_link_status_print(struct rte_eth_dev *eth_dev, struct rte_eth_link *link) { if (link && link->link_status) - plt_info("Port %d: Link Up - speed %u Mbps - %s", + plt_info("Port %d: Link Up - speed %u Mbps - %s - %s", (int)(eth_dev->data->port_id), (uint32_t)link->link_speed, link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? "full-duplex" - : "half-duplex"); + : "half-duplex", + rte_eth_link_type_to_str(link->link_type)); else - plt_info("Port %d: Link Down", (int)(eth_dev->data->port_id)); + plt_info("Port %d: Link Down - %s", (int)(eth_dev->data->port_id), + rte_eth_link_type_to_str(link->link_type)); } void @@ -103,6 +105,7 @@ cnxk_eth_dev_link_status_cb(struct roc_nix *nix, struct roc_nix_link_info *link) eth_link.link_speed = link->speed; eth_link.link_autoneg = RTE_ETH_LINK_AUTONEG; eth_link.link_duplex = link->full_duplex; + eth_link.link_type = dev->link_type; /* Print link info */ nix_link_status_print(eth_dev, ð_link); @@ -142,6 +145,7 @@ cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) link.link_autoneg = RTE_ETH_LINK_AUTONEG; if (info.full_duplex) link.link_duplex = info.full_duplex; + link.link_type = dev->link_type; } return rte_eth_linkstatus_set(eth_dev, &link); -- 2.34.1