> -----Original Message-----
> From: Nawal Kishor <nkis...@marvell.com>
> Sent: Monday, March 24, 2025 12:05 PM
> To: dev@dpdk.org; Nithin Kumar Dabilpuram <ndabilpu...@marvell.com>;
> Kiran Kumar Kokkilagadda <kirankum...@marvell.com>; Sunil Kumar Kori
> <sk...@marvell.com>; Satha Koteswara Rao Kottidi
> <skotesh...@marvell.com>; Harman Kalra <hka...@marvell.com>; Ashwin
> Sekhar T K <asek...@marvell.com>
> Cc: Jerin Jacob <jer...@marvell.com>; Nawal Kishor <nkis...@marvell.com>
> Subject: [PATCH v3] common/cnxk: fix aura offset
>
> Aura field width has reduced from 20 bits in cn10k/cn9k to 17 bits in cn20k.
> Adjust the setting of aura offset in NPA_LF_POOL_OP_INT register accordingly
> based on the platform.
>
> Fixes: 620fc02bf7eb ("common/cnxk: accommodate change in aura field
> width")
>
> Signed-off-by: Nawal Kishor <nkis...@marvell.com>
Updated the git commit as follows and applied to dpdk-next-net-mrvl/for-main.
Thanks
