Aura field width has reduced from 20 bits in cn10k/cn9k
to 17 bits in cn20k. Adjust the setting of aura offset in
NPA_LF_POOL_OP_INT register accordingly based on the platform.
Fixes: 620fc02bf7eb ("common/cnxk: accommodate change in aura field width")
Signed-off-by: Nawal Kishor <nkis...@marvell.com>
---
Changes in v3: Fixed checkpatch warnings.
drivers/common/cnxk/roc_npa_irq.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/roc_npa_irq.c
b/drivers/common/cnxk/roc_npa_irq.c
index 0a19319ebf..3142a40c8c 100644
--- a/drivers/common/cnxk/roc_npa_irq.c
+++ b/drivers/common/cnxk/roc_npa_irq.c
@@ -104,14 +104,15 @@ static inline uint8_t
npa_q_irq_get_and_clear(struct npa_lf *lf, uint32_t q, uint32_t off,
uint64_t mask)
{
- uint64_t reg, wdata;
+ uint64_t reg, wdata, shift;
uint8_t qint;
- wdata = (uint64_t)q << 44;
+ shift = roc_model_is_cn20k() ? 47 : 44;
+ wdata = (uint64_t)q << shift;
reg = roc_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));
if (reg & BIT_ULL(42) /* OP_ERR */) {
- plt_err("Failed execute irq get off=0x%x", off);
+ plt_err("Failed execute irq get off=0x%x reg=0x%" PRIu64, off,
reg);
return 0;
}
--
2.34.1
