From: Pawel Malinowski <pawel.malinow...@intel.com>
According to datasheet software ownership of SWSM.SWESMBI bit should not
exceed 100ms. Current implementation caused incorrect timeout counter
values, where each iteration equals 50us delay. Because of that driver was
allowed to wait for semaphore even for 1,5s. This might trigger DPC
timeout.
This implementation hardcodes value to 2000, which multiplied by 50us,
gives 100ms of possible wait time.
Fixes: 8cb7c57d9b3c ("net/igc: support device initialization")
Cc: sta...@dpdk.org
Signed-off-by: Pawel Malinowski <pawel.malinow...@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com>
---
drivers/net/intel/igc/base/igc_defines.h | 1 +
drivers/net/intel/igc/base/igc_i225.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/intel/igc/base/igc_defines.h
b/drivers/net/intel/igc/base/igc_defines.h
index 280570b157..3cb2f430c5 100644
--- a/drivers/net/intel/igc/base/igc_defines.h
+++ b/drivers/net/intel/igc/base/igc_defines.h
@@ -525,6 +525,7 @@
/* SW Semaphore Register */
#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
+#define IGC_SWSM_TIMEOUT 2000 /* Driver Semaphore max timeout
counter */
#define IGC_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
#define IGC_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
diff --git a/drivers/net/intel/igc/base/igc_i225.c
b/drivers/net/intel/igc/base/igc_i225.c
index 23c68a3948..7352ba240a 100644
--- a/drivers/net/intel/igc/base/igc_i225.c
+++ b/drivers/net/intel/igc/base/igc_i225.c
@@ -388,7 +388,7 @@ s32 igc_setup_copper_link_i225(struct igc_hw *hw)
static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)
{
u32 swsm;
- s32 timeout = hw->nvm.word_size + 1;
+ s32 timeout = IGC_SWSM_TIMEOUT;
s32 i = 0;
DEBUGFUNC("igc_get_hw_semaphore_i225");
--
2.43.5
