MSVC struct packing is not compatible with GCC. Replace macro
__rte_packed with __rte_packed_begin to push existing pack value
and set packing to 1-byte and macro __rte_packed_end to restore
the pack value prior to the push.
Macro __rte_packed_end is deliberately utilized to trigger a
MSVC compiler warning if no existing packing has been pushed allowing
easy identification of locations where the __rte_packed_begin is
missing.
Signed-off-by: Andre Muezerie <andre...@linux.microsoft.com>
---
drivers/crypto/caam_jr/caam_jr.c | 4 +-
drivers/crypto/caam_jr/caam_jr_desc.h | 64 ++++++++++----------
drivers/crypto/caam_jr/caam_jr_hw_specific.h | 48 +++++++--------
drivers/crypto/dpaa_sec/dpaa_sec.h | 12 ++--
drivers/crypto/ionic/ionic_crypto_if.h | 36 +++++------
drivers/crypto/mlx5/mlx5_crypto.h | 6 +-
drivers/crypto/mlx5/mlx5_crypto_gcm.c | 3 +-
drivers/crypto/qat/qat_sym.h | 7 ++-
drivers/crypto/qat/qat_sym_session.h | 4 +-
9 files changed, 94 insertions(+), 90 deletions(-)
diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c
index 4082b3f422..fedeefdf80 100644
--- a/drivers/crypto/caam_jr/caam_jr.c
+++ b/drivers/crypto/caam_jr/caam_jr.c
@@ -53,10 +53,10 @@ static enum sec_driver_state_e g_driver_state =
SEC_DRIVER_STATE_IDLE;
static int g_job_rings_no;
static int g_job_rings_max;
-struct sec_outring_entry {
+__rte_packed_begin struct sec_outring_entry {
phys_addr_t desc; /* Pointer to completed descriptor */
uint32_t status; /* Status for completed descriptor */
-} __rte_packed;
+} __rte_packed_end;
/* virtual address conversin when mempool support is available for ctx */
static inline phys_addr_t
diff --git a/drivers/crypto/caam_jr/caam_jr_desc.h
b/drivers/crypto/caam_jr/caam_jr_desc.h
index a4507613be..76cc07a94b 100644
--- a/drivers/crypto/caam_jr/caam_jr_desc.h
+++ b/drivers/crypto/caam_jr/caam_jr_desc.h
@@ -123,8 +123,8 @@
}
/* Union describing a descriptor header.
*/
-struct descriptor_header_s {
- union {
+__rte_packed_begin struct descriptor_header_s {
+ __rte_packed_begin union {
uint32_t word;
struct {
/* 4 */ unsigned int ctype:5;
@@ -162,15 +162,15 @@ struct descriptor_header_s {
/* 26 */ unsigned int res1:1;
/* 27 */ unsigned int ctype:5;
} jd;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end command;
+} __rte_packed_end;
/* Union describing a KEY command in a descriptor.
*/
-struct key_command_s {
- union {
+__rte_packed_begin struct key_command_s {
+ __rte_packed_begin union {
uint32_t word;
- struct {
+ __rte_packed_begin struct {
unsigned int ctype:5;
unsigned int cls:2;
unsigned int sgf:1;
@@ -182,30 +182,30 @@ struct key_command_s {
unsigned int tk:1;
unsigned int rsvd1:5;
unsigned int length:10;
- } __rte_packed field;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end field;
+ } __rte_packed_end command;
+} __rte_packed_end;
/* Union describing a PROTOCOL command
* in a descriptor.
*/
-struct protocol_operation_command_s {
- union {
+__rte_packed_begin struct protocol_operation_command_s {
+ __rte_packed_begin union {
uint32_t word;
- struct {
+ __rte_packed_begin struct {
unsigned int ctype:5;
unsigned int optype:3;
unsigned char protid;
unsigned short protinfo;
- } __rte_packed field;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end field;
+ } __rte_packed_end command;
+} __rte_packed_end;
/* Union describing a SEQIN command in a
* descriptor.
*/
-struct seq_in_command_s {
- union {
+__rte_packed_begin struct seq_in_command_s {
+ __rte_packed_begin union {
uint32_t word;
struct {
unsigned int ctype:5;
@@ -219,14 +219,14 @@ struct seq_in_command_s {
unsigned int res2:4;
unsigned int length:16;
} field;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end command;
+} __rte_packed_end;
/* Union describing a SEQOUT command in a
* descriptor.
*/
-struct seq_out_command_s {
- union {
+__rte_packed_begin struct seq_out_command_s {
+ __rte_packed_begin union {
uint32_t word;
struct {
unsigned int ctype:5;
@@ -238,11 +238,11 @@ struct seq_out_command_s {
unsigned int res2:5;
unsigned int length:16;
} field;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end command;
+} __rte_packed_end;
-struct load_command_s {
- union {
+__rte_packed_begin struct load_command_s {
+ __rte_packed_begin union {
uint32_t word;
struct {
unsigned int ctype:5;
@@ -253,23 +253,23 @@ struct load_command_s {
unsigned char offset;
unsigned char length;
} fields;
- } __rte_packed command;
-} __rte_packed;
+ } __rte_packed_end command;
+} __rte_packed_end;
/* Structure encompassing a general shared descriptor of maximum
* size (64 WORDs). Usually, other specific shared descriptor structures
* will be type-casted to this one
* this one.
*/
-struct __rte_aligned(64) sec_sd_t {
+__rte_packed_begin struct __rte_aligned(64) sec_sd_t {
uint32_t rsvd[MAX_DESC_SIZE_WORDS];
-} __rte_packed;
+} __rte_packed_end;
/* Structure encompassing a job descriptor which processes
* a single packet from a context. The job descriptor references
* a shared descriptor from a SEC context.
*/
-struct __rte_aligned(64) sec_job_descriptor_t {
+__rte_packed_begin struct __rte_aligned(64) sec_job_descriptor_t {
struct descriptor_header_s deschdr;
dma_addr_t sd_ptr;
struct seq_out_command_s seq_out;
@@ -280,6 +280,6 @@ struct __rte_aligned(64) sec_job_descriptor_t {
uint32_t in_ext_length;
struct load_command_s load_dpovrd;
uint32_t dpovrd;
-} __rte_packed;
+} __rte_packed_end;
#endif
diff --git a/drivers/crypto/caam_jr/caam_jr_hw_specific.h
b/drivers/crypto/caam_jr/caam_jr_hw_specific.h
index 6ee7f7cef3..d3c102bdf0 100644
--- a/drivers/crypto/caam_jr/caam_jr_hw_specific.h
+++ b/drivers/crypto/caam_jr/caam_jr_hw_specific.h
@@ -275,8 +275,8 @@ typedef enum sec_job_ring_state_e {
/* code or cmd block to caam */
struct sec_cdb {
- struct {
- union {
+ __rte_packed_begin struct {
+ __rte_packed_begin union {
uint32_t word;
struct {
#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
@@ -289,9 +289,9 @@ struct sec_cdb {
uint16_t rsvd63_48;
#endif
} field;
- } __rte_packed hi;
+ } __rte_packed_end hi;
- union {
+ __rte_packed_begin union {
uint32_t word;
struct {
#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
@@ -314,8 +314,8 @@ struct sec_cdb {
unsigned int rsvd31_30:2;
#endif
} field;
- } __rte_packed lo;
- } __rte_packed sh_hdr;
+ } __rte_packed_end lo;
+ } __rte_packed_end sh_hdr;
uint32_t sh_desc[SEC_JOB_DESCRIPTOR_SIZE];
};
@@ -390,54 +390,54 @@ struct sec_job_ring_t {
/* Union describing the possible error codes that
* can be set in the descriptor status word
*/
-union hw_error_code {
+__rte_packed_begin union hw_error_code {
uint32_t error;
- union {
- struct {
+ __rte_packed_begin union {
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t ssed_val:28;
- } __rte_packed value;
- struct {
+ } __rte_packed_end value;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t res:28;
- } __rte_packed no_status_src;
- struct {
+ } __rte_packed_end no_status_src;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t cha_id:4;
uint32_t err_id:4;
- } __rte_packed ccb_status_src;
- struct {
+ } __rte_packed_end ccb_status_src;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t offset:8;
- } __rte_packed jmp_halt_user_src;
- struct {
+ } __rte_packed_end jmp_halt_user_src;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t desc_err:8;
- } __rte_packed deco_src;
- struct {
+ } __rte_packed_end deco_src;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t res:17;
uint32_t naddr:3;
uint32_t desc_err:8;
- } __rte_packed jr_src;
- struct {
+ } __rte_packed_end jr_src;
+ __rte_packed_begin struct {
uint32_t ssrc:4;
uint32_t jmp:1;
uint32_t res:11;
uint32_t desc_idx:8;
uint32_t cond:8;
- } __rte_packed jmp_halt_cond_src;
- } __rte_packed error_desc;
-} __rte_packed;
+ } __rte_packed_end jmp_halt_cond_src;
+ } __rte_packed_end error_desc;
+} __rte_packed_end;
/* @brief Initialize a job ring/channel in SEC device.
* Write configuration register/s to properly initialize a job ring.
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h
b/drivers/crypto/dpaa_sec/dpaa_sec.h
index 64d9e22159..f8b0147845 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.h
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.h
@@ -62,8 +62,8 @@ enum dpaa_sec_op_type {
#define DPAA_SEC_MAX_DESC_SIZE 64
/* code or cmd block to caam */
struct sec_cdb {
- struct {
- union {
+ __rte_packed_begin struct {
+ __rte_packed_begin union {
uint32_t word;
struct {
#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
@@ -76,9 +76,9 @@ struct sec_cdb {
uint16_t rsvd63_48;
#endif
} field;
- } __packed hi;
+ } __rte_packed_end hi;
- union {
+ __rte_packed_begin union {
uint32_t word;
struct {
#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
@@ -101,8 +101,8 @@ struct sec_cdb {
unsigned int rsvd31_30:2;
#endif
} field;
- } __packed lo;
- } __packed sh_hdr;
+ } __rte_packed_end lo;
+ } __rte_packed_end sh_hdr;
uint32_t sh_desc[DPAA_SEC_MAX_DESC_SIZE];
};
diff --git a/drivers/crypto/ionic/ionic_crypto_if.h
b/drivers/crypto/ionic/ionic_crypto_if.h
index ea418f3d4b..eef2b6a6d9 100644
--- a/drivers/crypto/ionic/ionic_crypto_if.h
+++ b/drivers/crypto/ionic/ionic_crypto_if.h
@@ -263,13 +263,13 @@ struct iocpt_lif_setattr_cmd {
u8 opcode;
u8 attr;
__le16 lif_index;
- union {
+ __rte_packed_begin union {
u8 state;
char name[IOCPT_IFNAMSIZ];
__le64 features;
u8 stats_ctl;
u8 rsvd[60];
- } __rte_packed;
+ } __rte_packed_end;
};
/**
@@ -283,10 +283,10 @@ struct iocpt_lif_setattr_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
- union {
+ __rte_packed_begin union {
__le64 features;
u8 rsvd2[11];
- } __rte_packed;
+ } __rte_packed_end;
u8 color;
};
@@ -316,11 +316,11 @@ struct iocpt_lif_getattr_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
- union {
+ __rte_packed_begin union {
u8 state;
__le64 features;
u8 rsvd2[11];
- } __rte_packed;
+ } __rte_packed_end;
u8 color;
};
@@ -396,7 +396,7 @@ struct iocpt_q_identify_comp {
* @cq_ring_base: Completion queue ring base address
* @sg_ring_base: Scatter/Gather ring base address
*/
-struct iocpt_q_init_cmd {
+__rte_packed_begin struct iocpt_q_init_cmd {
u8 opcode;
u8 type;
__le16 lif_index;
@@ -417,7 +417,7 @@ struct iocpt_q_init_cmd {
__le64 cq_ring_base;
__le64 sg_ring_base;
u8 rsvd2[20];
-} __rte_packed;
+} __rte_packed_end;
/**
* struct iocpt_q_init_comp - Queue init command completion
@@ -469,7 +469,7 @@ enum iocpt_desc_opcode {
* @intr_ctx_addr: Completion interrupt context address
* @intr_ctx_data: Completion interrupt context data
*/
-struct iocpt_crypto_desc {
+__rte_packed_begin struct iocpt_crypto_desc {
uint8_t opcode;
uint8_t flags;
uint8_t num_src_dst_sgs;
@@ -481,7 +481,7 @@ struct iocpt_crypto_desc {
__le32 session_tag;
__le64 intr_ctx_addr;
__le64 intr_ctx_data;
-} __rte_packed;
+} __rte_packed_end;
static inline uint8_t iocpt_encode_nsge_src_dst(uint8_t src, uint8_t dst)
{
@@ -765,14 +765,14 @@ struct iocpt_log_event {
* @queue_count: Queue counts per queue-type
*/
union iocpt_lif_config {
- struct {
+ __rte_packed_begin struct {
u8 state;
u8 rsvd[3];
char name[IOCPT_IFNAMSIZ];
u8 rsvd2[12];
__le64 features;
__le32 queue_count[IOCPT_QTYPE_MAX];
- } __rte_packed;
+ } __rte_packed_end;
__le32 words[56];
};
@@ -876,14 +876,14 @@ union iocpt_dev_info_regs {
* @data: Opcode-specific side-data
*/
union iocpt_dev_cmd_regs {
- struct {
+ __rte_packed_begin struct {
u32 doorbell;
u32 done;
union iocpt_dev_cmd cmd;
union iocpt_dev_cmd_comp comp;
u8 rsvd[48];
u32 data[478];
- } __rte_packed;
+ } __rte_packed_end;
u32 words[512];
};
@@ -893,10 +893,10 @@ union iocpt_dev_cmd_regs {
* @devcmd: Device command registers
*/
union iocpt_dev_regs {
- struct {
+ __rte_packed_begin struct {
union iocpt_dev_info_regs info;
union iocpt_dev_cmd_regs devcmd;
- } __rte_packed;
+ } __rte_packed_end;
__le32 words[1024];
};
@@ -971,7 +971,7 @@ union iocpt_dev_identity {
* @config: LIF config struct with features, q counts
*/
union iocpt_lif_identity {
- struct {
+ __rte_packed_begin struct {
__le64 features;
u8 version;
@@ -980,7 +980,7 @@ union iocpt_lif_identity {
__le32 max_nb_sessions;
u8 rsvd2[120];
union iocpt_lif_config config;
- } __rte_packed;
+ } __rte_packed_end;
__le32 words[90];
};
diff --git a/drivers/crypto/mlx5/mlx5_crypto.h
b/drivers/crypto/mlx5/mlx5_crypto.h
index 547bb490e2..28eef9ef55 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.h
+++ b/drivers/crypto/mlx5/mlx5_crypto.h
@@ -32,9 +32,10 @@ enum mlx5_crypto_mode {
MLX5_CRYPTO_IPSEC_OPT,
};
+__rte_packed_begin
struct mlx5_crypto_ipsec_mem {
uint8_t mem[MLX5_CRYPTO_GCM_IPSEC_IV_SIZE];
-} __rte_packed;
+} __rte_packed_end;
struct mlx5_crypto_priv {
TAILQ_ENTRY(mlx5_crypto_priv) next;
@@ -108,6 +109,7 @@ struct mlx5_crypto_devarg_params {
enum mlx5_crypto_mode crypto_mode;
};
+__rte_packed_begin
struct mlx5_crypto_session {
union {
/**< AES-XTS configuration. */
@@ -145,7 +147,7 @@ struct mlx5_crypto_session {
/**< Initialisation Vector length. */
struct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */
uint32_t dek_id; /**< DEK ID */
-} __rte_packed;
+} __rte_packed_end;
struct mlx5_crypto_dek_ctx {
struct rte_crypto_sym_xform *xform;
diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
index cd21605bd2..b62e60854a 100644
--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
@@ -62,10 +62,11 @@ struct mlx5_crypto_gcm_data {
uint32_t dst_mkey;
};
+__rte_packed_begin
struct mlx5_crypto_gcm_tag_cpy_info {
void *digest;
uint8_t tag_len;
-} __rte_packed;
+} __rte_packed_end;
static struct rte_cryptodev_capabilities mlx5_crypto_gcm_caps[] = {
{
diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h
index eedf5de755..622161ad56 100644
--- a/drivers/crypto/qat/qat_sym.h
+++ b/drivers/crypto/qat/qat_sym.h
@@ -103,10 +103,10 @@
struct qat_sym_session;
-struct __rte_cache_aligned qat_sym_sgl {
+__rte_packed_begin struct __rte_cache_aligned qat_sym_sgl {
qat_sgl_hdr;
struct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER];
-} __rte_packed;
+} __rte_packed_end;
struct qat_sym_op_cookie {
struct qat_sym_sgl qat_sgl_src;
@@ -116,8 +116,9 @@ struct qat_sym_op_cookie {
union {
/* Used for Single-Pass AES-GMAC only */
struct {
+ __rte_packed_begin
alignas(RTE_CACHE_LINE_SIZE) struct
icp_qat_hw_cipher_algo_blk cd_cipher
- __rte_packed;
+ __rte_packed_end;
phys_addr_t cd_phys_addr;
} spc_gmac;
} opt;
diff --git a/drivers/crypto/qat/qat_sym_session.h
b/drivers/crypto/qat/qat_sym_session.h
index f2634774ec..2b85062170 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -92,7 +92,7 @@ typedef int (*qat_sym_build_request_t)(void *in_op, struct
qat_sym_session *ctx,
uint8_t *out_msg, void *op_cookie);
/* Common content descriptor */
-struct __rte_cache_aligned qat_sym_cd {
+__rte_packed_begin struct __rte_cache_aligned qat_sym_cd {
struct icp_qat_hw_cipher_algo_blk cipher;
union {
struct icp_qat_hw_auth_algo_blk hash;
@@ -100,7 +100,7 @@ struct __rte_cache_aligned qat_sym_cd {
struct icp_qat_hw_gen3_crc_cd crc_gen3;
struct icp_qat_hw_gen4_crc_cd crc_gen4;
};
-} __rte_packed;
+} __rte_packed_end;
struct qat_sym_session {
enum icp_qat_fw_la_cmd_id qat_cmd;
--
2.34.1
