Current RISC-V hardware (e.g. HiFive Unmatched) is still way too slow
compared to other architectures' counterparts. On the most powerful
RISC-V CPU available (SG2042), DPDK still fails with 4 timeouts:
```
Summary of Failures:
23/77 DPDK:fast-tests / eventdev_selftest_sw TIMEOUT
10.06s killed by signal 15 SIGTERM
56/77 DPDK:fast-tests / rib6_autotest TIMEOUT
10.04s
64/77 DPDK:fast-tests / spinlock_autotest TIMEOUT
10.06s killed by signal 15 SIGTERM
66/77 DPDK:fast-tests / table_autotest TIMEOUT
11.28s killed by signal 15 SIGTERM
```
On HiFive Unmatched, the longest test takes 53 seconds:
```
37/77 DPDK:fast-tests / lpm6_autotest OK
53.29s
```
Raising timeout to 60s on RISC-V target will help test effectiveness
on it.
Signed-off-by: Eric Long <[email protected]>
---
.mailmap | 1 +
app/test/suites/meson.build | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/.mailmap b/.mailmap
index 7334ad58a9..24f3f4a0cd 100644
--- a/.mailmap
+++ b/.mailmap
@@ -404,6 +404,7 @@ Erez Ferber <[email protected]> <[email protected]>
Erez Shitrit <[email protected]>
Eric Joyner <[email protected]>
Eric Kinzie <[email protected]> <[email protected]>
+Eric Long <[email protected]>
Eric Zhang <[email protected]>
Erik Gabriel Carrillo <[email protected]>
Erik Ziegenbalg <[email protected]>
diff --git a/app/test/suites/meson.build b/app/test/suites/meson.build
index 191702cf76..b74d1c4ad7 100644
--- a/app/test/suites/meson.build
+++ b/app/test/suites/meson.build
@@ -6,6 +6,11 @@
timeout_seconds = 600
timeout_seconds_fast = 10
+if arch_subdir == 'riscv'
+ # Current RISC-V machines are too slow to finish fast tests under 10s
+ timeout_seconds_fast = 60
+endif
+
test_no_huge_args = ['--no-huge', '-m', '2048']
has_hugepage = run_command(has_hugepages_cmd, check: true).stdout().strip() !=
'0'
message('hugepage availability: @0@'.format(has_hugepage))
--
2.47.0
