From: Pavan Nikhilesh <pbhagavat...@marvell.com>
Add SSO HWS a.k.a event port setup, release, link, unlink
functions.
Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
---
drivers/event/cnxk/cn10k_eventdev.c | 63 ++-----
drivers/event/cnxk/cn20k_eventdev.c | 174 ++++++++++++++++++++
drivers/event/cnxk/cn20k_eventdev.h | 26 +++
drivers/event/cnxk/cnxk_common.h | 55 +++++++
drivers/event/cnxk/cnxk_eventdev.h | 6 +-
drivers/event/cnxk/cnxk_eventdev_selftest.c | 6 +-
6 files changed, 276 insertions(+), 54 deletions(-)
create mode 100644 drivers/event/cnxk/cn20k_eventdev.h
create mode 100644 drivers/event/cnxk/cnxk_common.h
diff --git a/drivers/event/cnxk/cn10k_eventdev.c
b/drivers/event/cnxk/cn10k_eventdev.c
index 49805dd91d..43bc6c0bac 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -2,15 +2,16 @@
* Copyright(C) 2021 Marvell.
*/
+#include <rte_dmadev_pmd.h>
+
+#include "cn10k_cryptodev_ops.h"
+#include "cn10k_ethdev.h"
#include "cn10k_tx_worker.h"
#include "cn10k_worker.h"
-#include "cn10k_ethdev.h"
-#include "cn10k_cryptodev_ops.h"
+#include "cnxk_common.h"
+#include "cnxk_dma_event_dp.h"
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#include "cnxk_dma_event_dp.h"
-
-#include <rte_dmadev_pmd.h>
#define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)
\
deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
@@ -18,29 +19,6 @@
#define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)
\
enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
-static uint32_t
-cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
-{
- uint32_t wdata = 1;
-
- if (dev->deq_tmo_ns)
- wdata |= BIT(16);
-
- switch (dev->gw_mode) {
- case CN10K_GW_MODE_NONE:
- default:
- break;
- case CN10K_GW_MODE_PREF:
- wdata |= BIT(19);
- break;
- case CN10K_GW_MODE_PREF_WFE:
- wdata |= BIT(20) | BIT(19);
- break;
- }
-
- return wdata;
-}
-
static void *
cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
{
@@ -61,7 +39,7 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
ws->hws_id = port_id;
ws->swtag_req = 0;
- ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
+ ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev);
ws->gw_rdata = SSO_TT_EMPTY << 32;
ws->lmt_base = dev->sso.lmt_base;
ws->xae_waes = dev->sso.feat.xaq_wq_entries;
@@ -99,7 +77,7 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
ws->xaq_lmt = dev->xaq_lmt;
ws->fc_cache_space = (int64_t __rte_atomic *)dev->fc_cache_space;
ws->aw_lmt = ws->lmt_base;
- ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
+ ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev);
/* Set get_work timeout for HWS */
val = NSEC2USEC(dev->deq_tmo_ns);
@@ -220,12 +198,12 @@ cn10k_sso_hws_reset(void *arg, void *hws)
} while (pend_state & (BIT_ULL(58) | BIT_ULL(56)));
switch (dev->gw_mode) {
- case CN10K_GW_MODE_PREF:
- case CN10K_GW_MODE_PREF_WFE:
+ case CNXK_GW_MODE_PREF:
+ case CNXK_GW_MODE_PREF_WFE:
while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
;
break;
- case CN10K_GW_MODE_NONE:
+ case CNXK_GW_MODE_NONE:
default:
break;
}
@@ -504,18 +482,7 @@ cn10k_sso_dev_configure(const struct rte_eventdev
*event_dev)
if (rc < 0)
goto cnxk_rsrc_fini;
- switch (event_dev->data->dev_conf.preschedule_type) {
- default:
- case RTE_EVENT_PRESCHEDULE_NONE:
- dev->gw_mode = CN10K_GW_MODE_NONE;
- break;
- case RTE_EVENT_PRESCHEDULE:
- dev->gw_mode = CN10K_GW_MODE_PREF;
- break;
- case RTE_EVENT_PRESCHEDULE_ADAPTIVE:
- dev->gw_mode = CN10K_GW_MODE_PREF_WFE;
- break;
- }
+ dev->gw_mode =
cnxk_sso_hws_preschedule_get(event_dev->data->dev_conf.preschedule_type);
rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
cn10k_sso_hws_setup);
@@ -598,13 +565,13 @@ cn10k_sso_port_quiesce(struct rte_eventdev *event_dev,
void *port,
/* Check if we have work in PRF_WQE0, if so extract it. */
switch (dev->gw_mode) {
- case CN10K_GW_MODE_PREF:
- case CN10K_GW_MODE_PREF_WFE:
+ case CNXK_GW_MODE_PREF:
+ case CNXK_GW_MODE_PREF_WFE:
while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) &
BIT_ULL(63))
;
break;
- case CN10K_GW_MODE_NONE:
+ case CNXK_GW_MODE_NONE:
default:
break;
}
diff --git a/drivers/event/cnxk/cn20k_eventdev.c
b/drivers/event/cnxk/cn20k_eventdev.c
index b876c36806..611906a4f0 100644
--- a/drivers/event/cnxk/cn20k_eventdev.c
+++ b/drivers/event/cnxk/cn20k_eventdev.c
@@ -4,7 +4,87 @@
#include "roc_api.h"
+#include "cn20k_eventdev.h"
+#include "cnxk_common.h"
#include "cnxk_eventdev.h"
+#include "cnxk_worker.h"
+
+static void *
+cn20k_sso_init_hws_mem(void *arg, uint8_t port_id)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cn20k_sso_hws *ws;
+
+ /* Allocate event port memory */
+ ws = rte_zmalloc("cn20k_ws", sizeof(struct cn20k_sso_hws) +
RTE_CACHE_LINE_SIZE,
+ RTE_CACHE_LINE_SIZE);
+ if (ws == NULL) {
+ plt_err("Failed to alloc memory for port=%d", port_id);
+ return NULL;
+ }
+
+ /* First cache line is reserved for cookie */
+ ws = (struct cn20k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
+ ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
+ ws->hws_id = port_id;
+ ws->swtag_req = 0;
+ ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev);
+ ws->gw_rdata = SSO_TT_EMPTY << 32;
+ ws->xae_waes = dev->sso.feat.xaq_wq_entries;
+
+ return ws;
+}
+
+static int
+cn20k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link,
uint8_t profile)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cn20k_sso_hws *ws = port;
+
+ return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile,
0);
+}
+
+static int
+cn20k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link,
uint8_t profile)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cn20k_sso_hws *ws = port;
+
+ return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile,
0);
+}
+
+static void
+cn20k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cn20k_sso_hws *ws = hws;
+ uint64_t val;
+
+ ws->grp_base = grp_base;
+ ws->fc_mem = (int64_t __rte_atomic *)dev->fc_iova;
+ ws->xaq_lmt = dev->xaq_lmt;
+ ws->fc_cache_space = (int64_t __rte_atomic *)dev->fc_cache_space;
+ ws->aw_lmt = dev->sso.lmt_base;
+ ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev);
+
+ /* Set get_work timeout for HWS */
+ val = NSEC2USEC(dev->deq_tmo_ns);
+ val = val ? val - 1 : 0;
+ plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
+}
+
+static void
+cn20k_sso_hws_release(void *arg, void *hws)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cn20k_sso_hws *ws = hws;
+ uint16_t i, j;
+
+ for (i = 0; i < CNXK_SSO_MAX_PROFILES; i++)
+ for (j = 0; j < dev->nb_event_queues; j++)
+ roc_sso_hws_unlink(&dev->sso, ws->hws_id, &j, 1, i, 0);
+ memset(ws, 0, sizeof(*ws));
+}
static void
cn20k_sso_set_rsrc(void *arg)
@@ -60,11 +140,98 @@ cn20k_sso_dev_configure(const struct rte_eventdev
*event_dev)
if (rc < 0)
goto cnxk_rsrc_fini;
+ dev->gw_mode =
cnxk_sso_hws_preschedule_get(event_dev->data->dev_conf.preschedule_type);
+
+ rc = cnxk_setup_event_ports(event_dev, cn20k_sso_init_hws_mem,
cn20k_sso_hws_setup);
+ if (rc < 0)
+ goto cnxk_rsrc_fini;
+
+ /* Restore any prior port-queue mapping. */
+ cnxk_sso_restore_links(event_dev, cn20k_sso_hws_link);
+
+ dev->configured = 1;
+ rte_mb();
+
+ return 0;
cnxk_rsrc_fini:
roc_sso_rsrc_fini(&dev->sso);
+ dev->nb_event_ports = 0;
return rc;
}
+static int
+cn20k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
+ const struct rte_event_port_conf *port_conf)
+{
+
+ RTE_SET_USED(port_conf);
+ return cnxk_sso_port_setup(event_dev, port_id, cn20k_sso_hws_setup);
+}
+
+static void
+cn20k_sso_port_release(void *port)
+{
+ struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
+ struct cnxk_sso_evdev *dev;
+
+ if (port == NULL)
+ return;
+
+ dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
+ if (!gws_cookie->configured)
+ goto free;
+
+ cn20k_sso_hws_release(dev, port);
+ memset(gws_cookie, 0, sizeof(*gws_cookie));
+free:
+ rte_free(gws_cookie);
+}
+
+static int
+cn20k_sso_port_link_profile(struct rte_eventdev *event_dev, void *port, const
uint8_t queues[],
+ const uint8_t priorities[], uint16_t nb_links,
uint8_t profile)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ uint16_t hwgrp_ids[nb_links];
+ uint16_t link;
+
+ RTE_SET_USED(priorities);
+ for (link = 0; link < nb_links; link++)
+ hwgrp_ids[link] = queues[link];
+ nb_links = cn20k_sso_hws_link(dev, port, hwgrp_ids, nb_links, profile);
+
+ return (int)nb_links;
+}
+
+static int
+cn20k_sso_port_unlink_profile(struct rte_eventdev *event_dev, void *port,
uint8_t queues[],
+ uint16_t nb_unlinks, uint8_t profile)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ uint16_t hwgrp_ids[nb_unlinks];
+ uint16_t unlink;
+
+ for (unlink = 0; unlink < nb_unlinks; unlink++)
+ hwgrp_ids[unlink] = queues[unlink];
+ nb_unlinks = cn20k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks,
profile);
+
+ return (int)nb_unlinks;
+}
+
+static int
+cn20k_sso_port_link(struct rte_eventdev *event_dev, void *port, const uint8_t
queues[],
+ const uint8_t priorities[], uint16_t nb_links)
+{
+ return cn20k_sso_port_link_profile(event_dev, port, queues, priorities,
nb_links, 0);
+}
+
+static int
+cn20k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t
queues[],
+ uint16_t nb_unlinks)
+{
+ return cn20k_sso_port_unlink_profile(event_dev, port, queues,
nb_unlinks, 0);
+}
+
static struct eventdev_ops cn20k_sso_dev_ops = {
.dev_infos_get = cn20k_sso_info_get,
.dev_configure = cn20k_sso_dev_configure,
@@ -75,6 +242,13 @@ static struct eventdev_ops cn20k_sso_dev_ops = {
.queue_attr_set = cnxk_sso_queue_attribute_set,
.port_def_conf = cnxk_sso_port_def_conf,
+ .port_setup = cn20k_sso_port_setup,
+ .port_release = cn20k_sso_port_release,
+ .port_link = cn20k_sso_port_link,
+ .port_unlink = cn20k_sso_port_unlink,
+ .port_link_profile = cn20k_sso_port_link_profile,
+ .port_unlink_profile = cn20k_sso_port_unlink_profile,
+ .timeout_ticks = cnxk_sso_timeout_ticks,
};
static int
diff --git a/drivers/event/cnxk/cn20k_eventdev.h
b/drivers/event/cnxk/cn20k_eventdev.h
new file mode 100644
index 0000000000..5b6c558d5a
--- /dev/null
+++ b/drivers/event/cnxk/cn20k_eventdev.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#ifndef __CN20K_EVENTDEV_H__
+#define __CN20K_EVENTDEV_H__
+
+#define CN20K_SSO_DEFAULT_STASH_OFFSET -1
+#define CN20K_SSO_DEFAULT_STASH_LENGTH 2
+
+struct __rte_cache_aligned cn20k_sso_hws {
+ uint64_t base;
+ uint32_t gw_wdata;
+ uint64_t gw_rdata;
+ uint8_t swtag_req;
+ uint8_t hws_id;
+ /* Add Work Fastpath data */
+ alignas(RTE_CACHE_LINE_SIZE) int64_t __rte_atomic *fc_mem;
+ int64_t __rte_atomic *fc_cache_space;
+ uintptr_t aw_lmt;
+ uintptr_t grp_base;
+ uint16_t xae_waes;
+ int32_t xaq_lmt;
+};
+
+#endif /* __CN20K_EVENTDEV_H__ */
diff --git a/drivers/event/cnxk/cnxk_common.h b/drivers/event/cnxk/cnxk_common.h
new file mode 100644
index 0000000000..712d82bee7
--- /dev/null
+++ b/drivers/event/cnxk/cnxk_common.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#ifndef __CNXK_COMMON_H__
+#define __CNXK_COMMON_H__
+
+#include "cnxk_eventdev.h"
+#include "cnxk_worker.h"
+
+static uint32_t
+cnxk_sso_hws_prf_wdata(struct cnxk_sso_evdev *dev)
+{
+ uint32_t wdata = 1;
+
+ if (dev->deq_tmo_ns)
+ wdata |= BIT(16);
+
+ switch (dev->gw_mode) {
+ case CNXK_GW_MODE_NONE:
+ default:
+ break;
+ case CNXK_GW_MODE_PREF:
+ wdata |= BIT(19);
+ break;
+ case CNXK_GW_MODE_PREF_WFE:
+ wdata |= BIT(20) | BIT(19);
+ break;
+ }
+
+ return wdata;
+}
+
+static uint8_t
+cnxk_sso_hws_preschedule_get(uint8_t preschedule_type)
+{
+ uint8_t gw_mode = 0;
+
+ switch (preschedule_type) {
+ default:
+ case RTE_EVENT_PRESCHEDULE_NONE:
+ gw_mode = CNXK_GW_MODE_NONE;
+ break;
+ case RTE_EVENT_PRESCHEDULE:
+ gw_mode = CNXK_GW_MODE_PREF;
+ break;
+ case RTE_EVENT_PRESCHEDULE_ADAPTIVE:
+ gw_mode = CNXK_GW_MODE_PREF_WFE;
+ break;
+ }
+
+ return gw_mode;
+}
+
+#endif /* __CNXK_COMMON_H__ */
diff --git a/drivers/event/cnxk/cnxk_eventdev.h
b/drivers/event/cnxk/cnxk_eventdev.h
index ba08fa2173..4066497e6b 100644
--- a/drivers/event/cnxk/cnxk_eventdev.h
+++ b/drivers/event/cnxk/cnxk_eventdev.h
@@ -38,9 +38,9 @@
#define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0)
#define CN9K_DUAL_WS_NB_WS 2
-#define CN10K_GW_MODE_NONE 0
-#define CN10K_GW_MODE_PREF 1
-#define CN10K_GW_MODE_PREF_WFE 2
+#define CNXK_GW_MODE_NONE 0
+#define CNXK_GW_MODE_PREF 1
+#define CNXK_GW_MODE_PREF_WFE 2
#define CNXK_QOS_NORMALIZE(val, min, max, cnt)
\
(min + val / ((max + cnt - 1) / cnt))
diff --git a/drivers/event/cnxk/cnxk_eventdev_selftest.c
b/drivers/event/cnxk/cnxk_eventdev_selftest.c
index 311de3d92b..7a3262bcff 100644
--- a/drivers/event/cnxk/cnxk_eventdev_selftest.c
+++ b/drivers/event/cnxk/cnxk_eventdev_selftest.c
@@ -1568,15 +1568,15 @@ cnxk_sso_selftest(const char *dev_name)
if (roc_model_runtime_is_cn10k()) {
printf("Verifying CN10K workslot getwork mode none\n");
- dev->gw_mode = CN10K_GW_MODE_NONE;
+ dev->gw_mode = CNXK_GW_MODE_NONE;
if (cnxk_sso_testsuite_run(dev_name))
return rc;
printf("Verifying CN10K workslot getwork mode prefetch\n");
- dev->gw_mode = CN10K_GW_MODE_PREF;
+ dev->gw_mode = CNXK_GW_MODE_PREF;
if (cnxk_sso_testsuite_run(dev_name))
return rc;
printf("Verifying CN10K workslot getwork mode smart
prefetch\n");
- dev->gw_mode = CN10K_GW_MODE_PREF_WFE;
+ dev->gw_mode = CNXK_GW_MODE_PREF_WFE;
if (cnxk_sso_testsuite_run(dev_name))
return rc;
}
--
2.25.1
