Without memory barriers, there is no guarantee that the CPU will
actually wait until after the descriptor has been fully written before
loading descriptor data. In this case, it is possible that stale data is
read and acted on by the driver when processing TX or RX completions.
This change adds read memory barriers just after the generation bit is
read in both the RX and the TX path to ensure that the NIC has properly
passed ownership to the driver before descriptor data is read in full.
Note that memory barriers should not be needed after writing the RX
buffer queue/TX descriptor queue tails because rte_write32 includes an
implicit write memory barrier.
Fixes: 4022f9999f56 ("net/gve: support basic Tx data path for DQO")
Fixes: 45da16b5b181 ("net/gve: support basic Rx data path for DQO")
Cc: junfeng....@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Joshua Washington <joshw...@google.com>
Reviewed-by: Praveen Kaligineedi <pkaligine...@google.com>
Reviewed-by: Rushil Gupta <rush...@google.com>
---
drivers/net/gve/gve_rx_dqo.c | 2 ++
drivers/net/gve/gve_tx_dqo.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
index 5371bab77d..285c6ddd61 100644
--- a/drivers/net/gve/gve_rx_dqo.c
+++ b/drivers/net/gve/gve_rx_dqo.c
@@ -132,6 +132,8 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts)
if (rx_desc->generation != rxq->cur_gen_bit)
break;
+ rte_io_rmb();
+
if (unlikely(rx_desc->rx_error)) {
rxq->stats.errors++;
continue;
diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
index 731c287224..6984f92443 100644
--- a/drivers/net/gve/gve_tx_dqo.c
+++ b/drivers/net/gve/gve_tx_dqo.c
@@ -24,6 +24,8 @@ gve_tx_clean_dqo(struct gve_tx_queue *txq)
if (compl_desc->generation != txq->cur_gen_bit)
return;
+ rte_io_rmb();
+
compl_tag = rte_le_to_cpu_16(compl_desc->completion_tag);
aim_txq = txq->txqs[compl_desc->id];
--
2.47.0.rc0.187.ge670bccf7e-goog
