<snipped> > > > > For instance, in Neoverse N1 can disable the use of SLC as LLC (a BIOS > > setting) If SLC is not used as LLC, then your script would report the > > unified L2 > as an LLC. > > Does `disabling SLC as LLC` disable L3? I think not, and what you are > implying is > the ` ls -d /sys/bus/cpu/devices/cpu%u/cache/index[0-9] | sort -r …… ` will > return index2 and not index3. Is this the understanding? > It disables the use of SLC as an LLC for the CPUs and will return index2. Disable SLC as L3 is a feature in Arm CMN interconnects (SFONLY mode). When SLC is disabled as L3, firmware sets up ACPI PPTT to reflect this change. Using the PPTT kernel correctly enumerates cache IDs not showing an L3.
> > > I don't think that's what you are interested in. > My intention as shared is to `whether BIOS setting for CPU NUMA is enabled > or not, I would like to allow the end customer get the core complexes (tile) > which are under one group`. > So, if the `Last Level Cache` is L3 or L2 seen by OS, API allows the end user > to > get DPDK lcores sharing the last level cache. > > But as per the earlier communication, specific SoC does not behave when > some setting are done different. For AMD SoC case we are trying to help end > user with right setting with tuning guides as pointed by ` 12. How to get best > performance on AMD platform — Data Plane Development Kit 24.11.0-rc0 > documentation (dpdk.org) > <https://doc.dpdk.org/guides/linux_gsg/amd_platform.html> ` > > Can you please confirm if such tuning guides or recommended settings are > shared ? If not, can you please allow me to setup a technical call to sync on > the > same? > Currently there is no such document for Arm. But we would like to have one, there are some complexities too, not all SOC vendors use Arm's CMN interconnect. I would be happy to sync over a call. > > > > > 1. if there are specific SoC which do not populate the information > > > at all? If yes are they in DTS? > > > > This information is populated correctly for all SOCs, comment was on > > the script. > > Please note, I am not running any script. The command LCORE_GET_LLC is > executed using C function `open`. As per suggestion of Stephen we have > replied we will change to C function logic to get details. > Hope there is no longer confusion on this? > If this is implemented using sysfs, then it needs to handle caveats like SFONLY mode. Perhaps consulting /sys/bus/cpu/devices/cpu%u/cache/index[0-9]/type would help. However, I prefer using hwloc to get this information accurately. Thanks --wathsala
