Hi,
> -----邮件原件-----
> 发件人: Wathsala Wathawana Vithanage <wathsala.vithan...@arm.com>
> 发送时间: 2024年8月28日 4:56
> 收件人: Vipin Varghese <vipin.vargh...@amd.com>; ferruh.yi...@amd.com;
> dev@dpdk.org
> 抄送: nd <n...@arm.com>; nd <n...@arm.com>
> 主题: RE: [RFC 1/2] eal: add llc aware functions
>
> > -unsigned int rte_get_next_lcore(unsigned int i, int skip_main, int wrap)
> > +#define LCORE_GET_LLC \
> > + "ls -d /sys/bus/cpu/devices/cpu%u/cache/index[0-9] | sort -r
> > | grep -m1 index[0-9] | awk -F '[x]' '{print $2}' "
> >
>
> This won't work for some SOCs.
> How to ensure the index you got is for an LLC? Some SOCs may only show
> upper-level caches here, therefore cannot be use blindly without knowing the
> SOC.
> Also, unacceptable to execute a shell script, consider implementing in C.
Maybe：
For arm, maybe we can load MPIDR_EL1 register to achieve cpu cluster topology.
MPIDR_EL1 register bit meaning:
[23:16] AFF3 (Level 3 affinity)
[15:8] AFF2 (Level 2 affinity)
[7:0] AFF1 (Level 1 affinity)
[7:0] AFF0 (Level 0 affinity)
For x86, we can use apic_id:
Apic_id includes cluster id, die id, smt id and core id.
This bypass execute a shell script, and for arm and x86, we set different path
to implement this.
Best Regards
Feifei
> --wathsala
>
