From: Sergey Temerkhanov <sergey.temerkha...@intel.com>
Introduce functions enabling/disabling TX TS interrupts for the E822 and ETH56G
PHYs
Signed-off-by: Sergey Temerkhanov <sergey.temerkha...@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 73 +++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 4 ++
2 files changed, 77 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 2d042367a7..8f25d79a53 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2040,6 +2040,41 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8
port)
return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
}
+/**
+ * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
+ * @hw: pointer to the HW struct
+ * @port: the timestamp port
+ * @ena: enable or disable interrupt
+ * @threshold: interrupt threshold
+ *
+ * Configure TX timestamp interrupt for the specified port
+ */
+
+int
+ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
+{
+ int err;
+ u32 val;
+
+ err = ice_read_phy_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG,
+ &val);
+ if (err)
+ return err;
+
+ if (ena) {
+ val |= PHY_TS_INT_CONFIG_ENA_M;
+ val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
+ val |= ((threshold << PHY_TS_INT_CONFIG_THRESHOLD_S) &
+ PHY_TS_INT_CONFIG_THRESHOLD_M);
+ } else {
+ val &= ~PHY_TS_INT_CONFIG_ENA_M;
+ }
+
+ err = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG,
+ val);
+ return err;
+}
+
/**
* ice_ptp_clear_phy_offset_ready_eth56g - Clear PHY OFFSET_READY registers
* @hw: pointer to the HW struct
@@ -4502,6 +4537,44 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8
quad, u64 *tstamp_ready)
return 0;
}
+/**
+ * ice_phy_cfg_intr_e822 - Configure TX timestamp interrupt
+ * @hw: pointer to the HW struct
+ * @quad: the timestamp quad
+ * @ena: enable or disable interrupt
+ * @threshold: interrupt threshold
+ *
+ * Configure TX timestamp interrupt for the specified quad
+ */
+
+int
+ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
+{
+ int err;
+ u32 val;
+
+ err = ice_read_quad_reg_e822(hw, quad,
+ Q_REG_TX_MEM_GBL_CFG,
+ &val);
+ if (err)
+ return err;
+
+ if (ena) {
+ val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
+ val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
+ val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &
+ Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);
+ } else {
+ val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
+ }
+
+ err = ice_write_quad_reg_e822(hw, quad,
+ Q_REG_TX_MEM_GBL_CFG,
+ val);
+
+ return err;
+}
+
/* E810 functions
*
* The following functions operate on the E810 series devices which use
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 686246ab92..345d343a5a 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -259,6 +259,8 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool
soft_reset);
int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
+int
+ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
/* E810 family functions */
int ice_ptp_init_phy_e810(struct ice_hw *hw);
@@ -302,6 +304,8 @@ int
ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
+int
+ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
#define ICE_ETH56G_PLL_FREQ 800000000
#define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
--
2.43.0
