There is an issue of recursive header file includes in accessing the
idpf_hw structure. The controlq.h has the structure definition and osdep
header file needs that. The problem is the controlq.h also needs
the osdep header file contents, basically both dependent on each other.
Today it was resolved in CP by bringing their own idpf_hw definition but
that's not the case for other components which wanted to use the idpf_hw
directly from the shared code.
Signed-off-by: Soumyadeep Hore <soumyadeep.h...@intel.com>
---
drivers/common/idpf/base/idpf_controlq.h | 110 +------------------
drivers/common/idpf/base/idpf_controlq_api.h | 34 +++++-
drivers/common/idpf/base/idpf_type.h | 10 +-
3 files changed, 37 insertions(+), 117 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_controlq.h
b/drivers/common/idpf/base/idpf_controlq.h
index 80ca06e632..86ed3b7bcb 100644
--- a/drivers/common/idpf/base/idpf_controlq.h
+++ b/drivers/common/idpf/base/idpf_controlq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2023 Intel Corporation
+ * Copyright(c) 2001-2024 Intel Corporation
*/
#ifndef _IDPF_CONTROLQ_H_
@@ -18,7 +18,7 @@
#define IDPF_CTLQ_DESC_UNUSED(R) \
((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->ring_size) +
\
- (R)->next_to_clean - (R)->next_to_use - 1))
+ (R)->next_to_clean - (R)->next_to_use - 1))
/* Data type manipulation macros. */
#define IDPF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
@@ -96,111 +96,6 @@ struct idpf_mbxq_desc {
u32 pf_vf_id; /* used by CP when sending to PF */
};
-enum idpf_mac_type {
- IDPF_MAC_UNKNOWN = 0,
- IDPF_MAC_PF,
- IDPF_MAC_VF,
- IDPF_MAC_GENERIC
-};
-
-#define ETH_ALEN 6
-
-struct idpf_mac_info {
- enum idpf_mac_type type;
- u8 addr[ETH_ALEN];
- u8 perm_addr[ETH_ALEN];
-};
-
-#define IDPF_AQ_LINK_UP 0x1
-
-/* PCI bus types */
-enum idpf_bus_type {
- idpf_bus_type_unknown = 0,
- idpf_bus_type_pci,
- idpf_bus_type_pcix,
- idpf_bus_type_pci_express,
- idpf_bus_type_reserved
-};
-
-/* PCI bus speeds */
-enum idpf_bus_speed {
- idpf_bus_speed_unknown = 0,
- idpf_bus_speed_33 = 33,
- idpf_bus_speed_66 = 66,
- idpf_bus_speed_100 = 100,
- idpf_bus_speed_120 = 120,
- idpf_bus_speed_133 = 133,
- idpf_bus_speed_2500 = 2500,
- idpf_bus_speed_5000 = 5000,
- idpf_bus_speed_8000 = 8000,
- idpf_bus_speed_reserved
-};
-
-/* PCI bus widths */
-enum idpf_bus_width {
- idpf_bus_width_unknown = 0,
- idpf_bus_width_pcie_x1 = 1,
- idpf_bus_width_pcie_x2 = 2,
- idpf_bus_width_pcie_x4 = 4,
- idpf_bus_width_pcie_x8 = 8,
- idpf_bus_width_32 = 32,
- idpf_bus_width_64 = 64,
- idpf_bus_width_reserved
-};
-
-/* Bus parameters */
-struct idpf_bus_info {
- enum idpf_bus_speed speed;
- enum idpf_bus_width width;
- enum idpf_bus_type type;
-
- u16 func;
- u16 device;
- u16 lan_id;
- u16 bus_id;
-};
-
-/* Function specific capabilities */
-struct idpf_hw_func_caps {
- u32 num_alloc_vfs;
- u32 vf_base_id;
-};
-
-/* Define the APF hardware struct to replace other control structs as needed
- * Align to ctlq_hw_info
- */
-struct idpf_hw {
- /* Some part of BAR0 address space is not mapped by the LAN driver.
- * This results in 2 regions of BAR0 to be mapped by LAN driver which
- * will have its own base hardware address when mapped.
- */
- u8 *hw_addr;
- u8 *hw_addr_region2;
- u64 hw_addr_len;
- u64 hw_addr_region2_len;
-
- void *back;
-
- /* control queue - send and receive */
- struct idpf_ctlq_info *asq;
- struct idpf_ctlq_info *arq;
-
- /* subsystem structs */
- struct idpf_mac_info mac;
- struct idpf_bus_info bus;
- struct idpf_hw_func_caps func_caps;
-
- /* pci info */
- u16 device_id;
- u16 vendor_id;
- u16 subsystem_device_id;
- u16 subsystem_vendor_id;
- u8 revision_id;
- bool adapter_stopped;
-
- LIST_HEAD_TYPE(list_head, idpf_ctlq_info) cq_list_head;
-};
-
int idpf_ctlq_alloc_ring_res(struct idpf_hw *hw,
struct idpf_ctlq_info *cq);
@@ -210,4 +105,5 @@ void idpf_ctlq_dealloc_ring_res(struct idpf_hw *hw, struct
idpf_ctlq_info *cq);
void *idpf_alloc_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem,
u64 size);
void idpf_free_dma_mem(struct idpf_hw *hw, struct idpf_dma_mem *mem);
+
#endif /* _IDPF_CONTROLQ_H_ */
diff --git a/drivers/common/idpf/base/idpf_controlq_api.h
b/drivers/common/idpf/base/idpf_controlq_api.h
index bce5187981..3ad2da5b2e 100644
--- a/drivers/common/idpf/base/idpf_controlq_api.h
+++ b/drivers/common/idpf/base/idpf_controlq_api.h
@@ -154,6 +154,36 @@ enum idpf_mbx_opc {
idpf_mbq_opc_send_msg_to_peer_drv = 0x0804,
};
+/* Define the APF hardware struct to replace other control structs as needed
+ * Align to ctlq_hw_info
+ */
+struct idpf_hw {
+ /* Some part of BAR0 address space is not mapped by the LAN driver.
+ * This results in 2 regions of BAR0 to be mapped by LAN driver which
+ * will have its own base hardware address when mapped.
+ */
+ u8 *hw_addr;
+ u8 *hw_addr_region2;
+ u64 hw_addr_len;
+ u64 hw_addr_region2_len;
+
+ void *back;
+
+ /* control queue - send and receive */
+ struct idpf_ctlq_info *asq;
+ struct idpf_ctlq_info *arq;
+
+ /* pci info */
+ u16 device_id;
+ u16 vendor_id;
+ u16 subsystem_device_id;
+ u16 subsystem_vendor_id;
+ u8 revision_id;
+ bool adapter_stopped;
+
+ LIST_HEAD_TYPE(list_head, idpf_ctlq_info) cq_list_head;
+};
+
/* API supported for control queue management */
/* Will init all required q including default mb. "q_info" is an array of
* create_info structs equal to the number of control queues to be created.
@@ -161,10 +191,12 @@ enum idpf_mbx_opc {
#ifdef NVME_CPF
int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
struct idpf_ctlq_create_info *q_info, struct idpf_ctlq_info
**ctlq);
+
#else
int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
struct idpf_ctlq_create_info *q_info);
-#endif
+
+#endif /* NVME_CPF */
/* Allocate and initialize a single control queue, which will be added to the
* control queue list; returns a handle to the created control queue
diff --git a/drivers/common/idpf/base/idpf_type.h
b/drivers/common/idpf/base/idpf_type.h
index a22d28f448..26ae9df147 100644
--- a/drivers/common/idpf/base/idpf_type.h
+++ b/drivers/common/idpf/base/idpf_type.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2023 Intel Corporation
+ * Copyright(c) 2001-2024 Intel Corporation
*/
#ifndef _IDPF_TYPE_H_
@@ -80,14 +80,6 @@ struct idpf_ctlq_size {
u16 arq_ring_size;
};
-/* Temporary definition to compile - TBD if needed */
-struct idpf_arq_event_info {
- struct idpf_ctlq_desc desc;
- u16 msg_len;
- u16 buf_len;
- u8 *msg_buf;
-};
-
struct idpf_get_set_rss_key_data {
u8 standard_rss_key[0x28];
u8 extended_hash_key[0xc];
--
2.43.0
