[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Selwin Sebastian<selwin.sebast...@amd.com>
-----Original Message-----
From: Ande, Venkat Kumar <venkatkumar.a...@amd.com>
Sent: Tuesday, May 7, 2024 6:13 PM
To: dev@dpdk.org
Cc: Sebastian, Selwin <selwin.sebast...@amd.com>; Ande, Venkat Kumar
<venkatkumar.a...@amd.com>; sta...@dpdk.org
Subject: [PATCH v2 11/25] net/axgbe: flow Tx Ctrl Registers are h/w version
dependent
There is difference in the TX Flow Control registers (TFCR) between the
revisions of the hardware. The older revisions of hardware used to have single
register per queue. Whereas, the newer revision of hardware (from ver 30H
onwards) have one register per priority.
Without the fix the user will face problem in TX operation on new 30H HW
Fixes: 7c4158a5b592 ("net/axgbe: add DMA programming and start/stop")
Cc: sta...@dpdk.org
Signed-off-by: Venkat Kumar Ande <venkatkumar.a...@amd.com>
---
drivers/net/axgbe/axgbe_dev.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 9b0073eea6..5233633a53 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -269,20 +269,28 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int
speed)
return 0;
}
+static unsigned int axgbe_get_fc_queue_count(struct axgbe_port *pdata)
+{
+ unsigned int max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
+
+ /* From MAC ver 30H the TFCR is per priority, instead of per queue */
+ if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)
+ return max_q_count;
+ else
+ return (RTE_MIN(pdata->tx_q_count, max_q_count)); }
+
static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata) {
- unsigned int max_q_count, q_count;
unsigned int reg, reg_val;
- unsigned int i;
+ unsigned int i, q_count;
/* Clear MTL flow control */
for (i = 0; i < pdata->rx_q_count; i++)
AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
/* Clear MAC flow control */
- max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
- q_count = RTE_MIN(pdata->tx_q_count,
- max_q_count);
+ q_count = axgbe_get_fc_queue_count(pdata);
reg = MAC_Q0TFCR;
for (i = 0; i < q_count; i++) {
reg_val = AXGMAC_IOREAD(pdata, reg);
@@ -297,9 +305,8 @@ static int axgbe_disable_tx_flow_control(struct axgbe_port
*pdata)
static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata) {
- unsigned int max_q_count, q_count;
unsigned int reg, reg_val;
- unsigned int i;
+ unsigned int i, q_count;
/* Set MTL flow control */
for (i = 0; i < pdata->rx_q_count; i++) { @@ -316,9 +323,7 @@ static
int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)
}
/* Set MAC flow control */
- max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
- q_count = RTE_MIN(pdata->tx_q_count,
- max_q_count);
+ q_count = axgbe_get_fc_queue_count(pdata);
reg = MAC_Q0TFCR;
for (i = 0; i < q_count; i++) {
reg_val = AXGMAC_IOREAD(pdata, reg);
--
2.34.1
