Hi,
> -----Original Message-----
> From: Gregory Etelson <getel...@nvidia.com>
> Sent: Wednesday, March 6, 2024 9:39 AM
> To: dev@dpdk.org
> Cc: Gregory Etelson <getel...@nvidia.com>; Maayan Kashani
> <mkash...@nvidia.com>; Raslan Darawsheh <rasl...@nvidia.com>; Dariusz
> Sosnowski <dsosnow...@nvidia.com>; Slava Ovsiienko
> <viachesl...@nvidia.com>; Ori Kam <or...@nvidia.com>; Suanming Mou
> <suanmi...@nvidia.com>; Matan Azrad <ma...@nvidia.com>
> Subject: [PATCH] net/mlx5: fix pattern template size validation
>
> PMD running in HWS FDB mode can be configured to steer group 0 to FW.
> In that case PMD activates legacy DV pattern processing.
> There are control flows that require HWS pattern processing in group 0.
>
> Pattern template validation tried to create a matcher both in group 0 and HWS
> group.
> As the result, during group 0 validation HWS tuned pattern was processed as
> DV.
>
> The patch removed pattern validation for group 0.
>
> Fixes: f3aadd103358 ("net/mlx5: improve pattern template validation")
> Signed-off-by: Gregory Etelson <getel...@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
