Add cache guard to per-lcore data structures to prevent false sharing
in scenarios where a next-N-lines (or similar) hardware prefetcher is
used.

Signed-off-by: Mattias Rönnblom <mattias.ronnb...@ericsson.com>
---
 lib/dispatcher/rte_dispatcher.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/dispatcher/rte_dispatcher.c b/lib/dispatcher/rte_dispatcher.c
index 95dd41b818..f546d75c0b 100644
--- a/lib/dispatcher/rte_dispatcher.c
+++ b/lib/dispatcher/rte_dispatcher.c
@@ -48,6 +48,7 @@ struct rte_dispatcher_lcore {
        struct rte_dispatcher_lcore_port ports[EVD_MAX_PORTS_PER_LCORE];
        struct rte_dispatcher_handler handlers[EVD_MAX_HANDLERS];
        struct rte_dispatcher_stats stats;
+       RTE_CACHE_GUARD;
 } __rte_cache_aligned;
 
 struct rte_dispatcher {
-- 
2.34.1

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