> On 9/25/2023 7:06 AM, Chaoyong He wrote: > > From: Shihong Wang <shihong.w...@corigine.com> > > > > Add TLV capabilities to the BAR, TLVs is fit for expressing > > capabilities of applications running on programmable hardware. > > > > Here application referred is bitstream or FW, right? Yes, it is.
> And PCIe BAR is used to exchange the capability information. > Not for this patch, but I wonder is there a value to add this kind of parsing > to the > PCI code, if it is a generic usage, Chaoyong what do you think? Basically, it does have value to do that, the kernel driver already have these logics for a long time and using it for some features. For our PMD, it's the first time we import this and the main reason is we need to support the mailbox channel between driver and CoreNIC firmware. The mailbox channel is needed for IPsec and other features we will try to merge in the near future. I have to admit the ` nfp_net_tlv_caps_parse()` function now seems does have some unrelated logics, I will try to remove them in the next version patch. Do you think it's okay? > > Declares a TLV capability start at offset 0x58, up to 0x0d90. > > The used space can be wrapped with RESERVED. > > > > Signed-off-by: Shihong Wang <shihong.w...@corigine.com> > > Signed-off-by: Chang Miao <chang.m...@corigine.com> > > Reviewed-by: Chaoyong He <chaoyong...@corigine.com> > > > > <...>
