> -----Original Message-----
> From: David Marchand <david.march...@redhat.com>
> Sent: Thursday, September 14, 2023 8:36 PM
> To: dev@dpdk.org
> Cc: tho...@monjalon.net; ferruh.yi...@amd.com; Xia, Chenbo
> <chenbo....@intel.com>; nipun.gu...@amd.com; Richardson, Bruce
> <bruce.richard...@intel.com>; Sevincer, Abdullah
> <abdullah.sevin...@intel.com>; Gaetan Rivet <gr...@u256.net>
> Subject: [PATCH v3 13/15] pci: define some PRI constants
>
> Define some PCI PRI extended feature constants and use them in existing
> drivers.
>
> Signed-off-by: David Marchand <david.march...@redhat.com>
> Acked-by: Bruce Richardson <bruce.richard...@intel.com>
> ---
> drivers/event/dlb2/pf/dlb2_main.c | 11 ++++-------
> lib/pci/rte_pci.h | 5 +++++
> 2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/event/dlb2/pf/dlb2_main.c
> b/drivers/event/dlb2/pf/dlb2_main.c
> index 8e729d1964..187a356c24 100644
> --- a/drivers/event/dlb2/pf/dlb2_main.c
> +++ b/drivers/event/dlb2/pf/dlb2_main.c
> @@ -27,9 +27,6 @@
> #define NO_OWNER_VF 0 /* PF ONLY! */
> #define NOT_VF_REQ false /* PF ONLY! */
>
> -#define DLB2_PCI_PRI_CTRL_ENABLE 0x1
> -#define DLB2_PCI_PRI_ALLOC_REQ 0xC
> -#define DLB2_PCI_PRI_CTRL 0x4
> #define DLB2_PCI_ERR_ROOT_STATUS 0x30
> #define DLB2_PCI_ERR_COR_STATUS 0x10
> #define DLB2_PCI_ERR_UNCOR_STATUS 0x4
> @@ -257,7 +254,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> pri_cap_offset = rte_pci_find_ext_capability(pdev, off);
>
> if (pri_cap_offset >= 0) {
> - off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;
> + off = pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ;
> if (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) != 4)
> pri_reqs_dword = 0;
> }
> @@ -377,9 +374,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> }
>
> if (pri_cap_offset >= 0) {
> - pri_ctrl_word = DLB2_PCI_PRI_CTRL_ENABLE;
> + pri_ctrl_word = RTE_PCI_PRI_CTRL_ENABLE;
>
> - off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;
> + off = pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ;
> ret = rte_pci_write_config(pdev, &pri_reqs_dword, 4, off);
> if (ret != 4) {
> DLB2_LOG_ERR("[%s()] failed to write the pcie config
> space at offset %d\n",
> @@ -387,7 +384,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> return ret;
> }
>
> - off = pri_cap_offset + DLB2_PCI_PRI_CTRL;
> + off = pri_cap_offset + RTE_PCI_PRI_CTRL;
> ret = rte_pci_write_config(pdev, &pri_ctrl_word, 2, off);
> if (ret != 2) {
> DLB2_LOG_ERR("[%s()] failed to write the pcie config
> space at offset %d\n",
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index a6c52a232d..6bbcad20f2 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -123,6 +123,11 @@ extern "C" {
> #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
> #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
>
> +/* Page Request Interface (RTE_PCI_EXT_CAP_ID_PRI) */
> +#define RTE_PCI_PRI_CTRL 0x04 /* PRI control register */
> +#define RTE_PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
> +#define RTE_PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed
> */
> +
> /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
> #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
> #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
> --
> 2.41.0
Reviewed-by: Chenbo Xia <chenbo....@intel.com>
