Define some PCI Power Management constants and use them in existing
drivers.
Signed-off-by: David Marchand <david.march...@redhat.com>
---
drivers/net/bnx2x/bnx2x.c | 17 +++++++++--------
drivers/net/bnx2x/bnx2x.h | 5 -----
lib/pci/rte_pci.h | 6 ++++++
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index e3f14400cc..faf061beba 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -5843,17 +5843,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc
*sc, uint8_t state)
return 0;
}
- pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
+ pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + RTE_PCI_PM_CTRL), &pmcsr,
2);
switch (state) {
case PCI_PM_D0:
pci_write_word(sc,
(sc->devinfo.pcie_pm_cap_reg +
- PCIR_POWER_STATUS),
- ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
+ RTE_PCI_PM_CTRL),
+ ((pmcsr & ~RTE_PCI_PM_CTRL_STATE_MASK) |
RTE_PCI_PM_CTRL_PME_STATUS));
- if (pmcsr & PCIM_PSTAT_DMASK) {
+ if (pmcsr & RTE_PCI_PM_CTRL_STATE_MASK) {
/* delay required during transition out of D3hot */
DELAY(20000);
}
@@ -5866,16 +5866,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc
*sc, uint8_t state)
return 0;
}
- pmcsr &= ~PCIM_PSTAT_DMASK;
- pmcsr |= PCIM_PSTAT_D3;
+ pmcsr &= ~RTE_PCI_PM_CTRL_STATE_MASK;
+ /* D3 power state */
+ pmcsr |= 0x3;
if (sc->wol) {
- pmcsr |= PCIM_PSTAT_PMEENABLE;
+ pmcsr |= RTE_PCI_PM_CTRL_PME_ENABLE;
}
pci_write_long(sc,
(sc->devinfo.pcie_pm_cap_reg +
- PCIR_POWER_STATUS), pmcsr);
+ RTE_PCI_PM_CTRL), pmcsr);
/*
* No more memory access after this point until device is
brought back
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 60af75d336..1efa166316 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -41,11 +41,6 @@
#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
-#define PCIR_POWER_STATUS PCI_PM_CTRL
-#define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
-#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
-#define PCIM_PSTAT_D3 0x3
-#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
#else
#include <dev/pci/pcireg.h>
#endif
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index 429904cff9..b7e1ff5d78 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -56,6 +56,12 @@ extern "C" {
#define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define RTE_PCI_CAP_SIZEOF 4
+/* Power Management Registers */
+#define RTE_PCI_PM_CTRL 4 /* PM control and
status register */
+#define RTE_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to
D3) */
+#define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
+#define RTE_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
+
/* MSI-X registers */
#define RTE_PCI_MSIX_FLAGS 2 /* Message Control */
#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */
--
2.41.0
