On Tue, Feb 7, 2023 at 2:34 AM Stephen Hemminger
<step...@networkplumber.org> wrote:
>
> On Tue, 7 Feb 2023 01:54:43 +0530
> <jer...@marvell.com> wrote:
>
> > +static struct rte_ml_dev ml_devices[RTE_MLDEV_MAX_DEVS];
> >
>
> This will reserve space for 64 devices, but almost all users
> will only have one. Maybe a level of indirection and allocate as needed?
As Thomas suggested, I will add something similar to rte_gpu_init()
>
> You could even use a single allocation for the pmd and device private
> data portion.
>
> > + */
> > +struct rte_ml_dev_data {
> > + /** Unique identifier name. */
> > + char name[RTE_ML_STR_MAX];
>
>
> Why is name first, it is the least used field. Might want it to be last
> for cache locality.
It is slowpath, does not matter. But there is no harm in moving end of
it. I will move to end of the structure.
>
> > + /** Reserved for future fields */
> > + uint64_t reserved[3];
>
> Reserved fields have been a problem in the past.
Will remove it.
> Why do this? Are thy just available pad elements to be cache line size?
Yes.
>
> And why bother being cache aligned for an info struct?
We can remove it. Will removing reserved and cache aligned.
>
