Allow building generic arm64 target using config/arm/arm64_armv8_linux_*
config which works on both cn9k and cn10k by relaxing cache line size
requirements a bit.
While at it move cache line checks to common place.
Signed-off-by: Tomasz Duszynski <tduszyn...@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jer...@marvell.com>
---
drivers/common/cnxk/roc_dev.c | 26 ++++++++++++++++++++++++++
drivers/event/cnxk/cn10k_eventdev.c | 5 -----
drivers/event/cnxk/cn9k_eventdev.c | 5 -----
drivers/net/cnxk/cn10k_ethdev.c | 5 -----
drivers/net/cnxk/cn9k_ethdev.c | 5 -----
5 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 9a869698c4..09199ac2ff 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -1094,6 +1094,29 @@ dev_lmt_setup(struct dev *dev)
return -errno;
}
+static bool
+dev_cache_line_size_valid(void)
+{
+ if (roc_model_is_cn9k()) {
+ if (PLT_CACHE_LINE_SIZE != 128) {
+ plt_err("Cache line size of %d is wrong for CN9K",
+ PLT_CACHE_LINE_SIZE);
+ return false;
+ }
+ } else if (roc_model_is_cn10k()) {
+ if (PLT_CACHE_LINE_SIZE == 128) {
+ plt_warn("Cache line size of %d might affect
performance",
+ PLT_CACHE_LINE_SIZE);
+ } else if (PLT_CACHE_LINE_SIZE != 64) {
+ plt_err("Cache line size of %d is wrong for CN10K",
+ PLT_CACHE_LINE_SIZE);
+ return false;
+ }
+ }
+
+ return true;
+}
+
int
dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
{
@@ -1102,6 +1125,9 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
uintptr_t vf_mbase = 0;
uint64_t intr_offset;
+ if (!dev_cache_line_size_valid())
+ return -EFAULT;
+
bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
bar4 = (uintptr_t)pci_dev->mem_resource[4].addr;
if (bar2 == 0 || bar4 == 0) {
diff --git a/drivers/event/cnxk/cn10k_eventdev.c
b/drivers/event/cnxk/cn10k_eventdev.c
index 77f0c28160..25d01fd90a 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -963,11 +963,6 @@ cn10k_sso_init(struct rte_eventdev *event_dev)
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
int rc;
- if (RTE_CACHE_LINE_SIZE != 64) {
- plt_err("Driver not compiled for CN10K");
- return -EFAULT;
- }
-
rc = roc_plt_init();
if (rc < 0) {
plt_err("Failed to initialize platform model");
diff --git a/drivers/event/cnxk/cn9k_eventdev.c
b/drivers/event/cnxk/cn9k_eventdev.c
index 4d45f02c1c..6fef15e352 100644
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -1193,11 +1193,6 @@ cn9k_sso_init(struct rte_eventdev *event_dev)
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
int rc;
- if (RTE_CACHE_LINE_SIZE != 128) {
- plt_err("Driver not compiled for CN9K");
- return -EFAULT;
- }
-
rc = roc_plt_init();
if (rc < 0) {
plt_err("Failed to initialize platform model");
diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 4cd82af7e5..33f61743f9 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -759,11 +759,6 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
struct cnxk_eth_dev *dev;
int rc;
- if (RTE_CACHE_LINE_SIZE != 64) {
- plt_err("Driver not compiled for CN10K");
- return -EFAULT;
- }
-
rc = roc_plt_init();
if (rc) {
plt_err("Failed to initialize platform model, rc=%d", rc);
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index a388b3a8a6..fb34d20759 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -689,11 +689,6 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
struct cnxk_eth_dev *dev;
int rc;
- if (RTE_CACHE_LINE_SIZE != 128) {
- plt_err("Driver not compiled for CN9K");
- return -EFAULT;
- }
-
rc = roc_plt_init();
if (rc) {
plt_err("Failed to initialize platform model, rc=%d", rc);
--
2.25.1
