<snip>
> >>> +__rte_experimental
> >>> +static inline bool
> >>> +rte_seqlock_read_retry(const rte_seqlock_t *seqlock, uint32_t
> >>> +begin_sn) {
> >>> + uint32_t end_sn;
> >>> +
> >>> + /* An odd sequence number means the protected data was being
> >>> + * modified already at the point of the rte_seqlock_read_begin()
> >>> + * call.
> >>> + */
> >>> + if (unlikely(begin_sn & 1))
> >>> + return true;
> >>> +
> >>> + /* make sure the data loads happens before the sn load */
> >>> + rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
> >>
> >> In ARMv8, the rte_atomic_thread_fence(__ATOMIC_ACQUIRE) and
> >> rte_smp_rmb() both output 'dma ishld'
> >> Suggest use rte_smp_rmb(), please see below comment.
> > rte_smp_xxx APIs are deprecated. Please check [1]
> >
> > [1] https://www.dpdk.org/blog/2021/03/26/dpdk-adopts-the-c11-memory-
> model/
>
> Got it, thanks
>
> And I have a question about ARM: why can't find the
> parameter(rte_atomic_thread_fence(?)) corresponding to 'dmb ishst'?
> I tried __ATOMIC_RELEASE/ACQ_REL/SEQ_CST and can't find it.
'dmb ishst' prevents store-store reordering. However, '__atomic_thread_fence'
(with various memory ordering) requires more stronger barrier [1].
[1] https://preshing.com/20130922/acquire-and-release-fences/
>
> >
> > <snip>
> >
