This patch removes a redundant assert in mlx5_tx_packet_multi_tso().
That assert assured that the amount of bytes requested to be inlined
is greater than or equal to the minimum amount of bytes required
to be inlined. This requirement is either derived from the NIC
inlining mode or configured through devargs. When using TSO this
requirement can be disregarded, because on all NICs it is satisfied by TSO
inlining requirements, since TSO requires L2, L3, and L4 headers to be
inlined.
Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
Cc: viachesl...@nvidia.com
Cc: sta...@dpdk.org
Signed-off-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
---
drivers/net/mlx5/mlx5_tx.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index 099e72935a..398cadfeaa 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -1710,7 +1710,6 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data
*__rte_restrict txq,
inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
inlen > (dlen + vlan)))
return MLX5_TXCMP_CODE_ERROR;
- MLX5_ASSERT(inlen >= txq->inlen_mode);
/*
* Check whether there are enough free WQEBBs:
* - Control Segment
--
2.25.1
