On 12/9/2021 9:13 AM, Nithin Dabilpuram wrote:
Change the order of frag sizes and infos to match HW
implementation.

Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelum...@marvell.com>
---
  drivers/common/cnxk/hw/cpt.h | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 919f842..99a900c 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -286,10 +286,10 @@ struct cpt_frag_info_s {
        union {
                uint64_t u64;
                struct {
-                       union cpt_frag_info f3;
-                       union cpt_frag_info f2;
-                       union cpt_frag_info f1;
                        union cpt_frag_info f0;
+                       union cpt_frag_info f1;
+                       union cpt_frag_info f2;
+                       union cpt_frag_info f3;
                };
        } w0;
@@ -297,10 +297,10 @@ struct cpt_frag_info_s {
        union {
                uint64_t u64;
                struct {
-                       uint16_t frag_size3;
-                       uint16_t frag_size2;
-                       uint16_t frag_size1;
                        uint16_t frag_size0;
+                       uint16_t frag_size1;
+                       uint16_t frag_size2;
+                       uint16_t frag_size3;


If this is related to the endianness requirement of the HW, it can be good to 
comment
this in the code.

                };
        } w1;
  };

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