On Thu, Dec 9, 2021 at 2:44 PM Nithin Dabilpuram
<ndabilpu...@marvell.com> wrote:
>
> From: Harman Kalra <hka...@marvell.com>
>
> LF's error debug registers like NIX_LF_SQ_OP_ERR_DBG,
> NIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug
> info for an error detected during LMT operation or meta
> enqueue or after meta enqueue granted respectively. HW
> sets a valid bit when info is captured and SW is expected
> to clear this valid bit by writing 1, else these registers
> will show stale values of first interrupt when occurred and
> will never update with subsequent interrupts.
>
> Signed-off-by: Harman Kalra <hka...@marvell.com>
Acked-by: Jerin Jacob <jer...@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> ---
> drivers/common/cnxk/roc_nix_irq.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_irq.c
> b/drivers/common/cnxk/roc_nix_irq.c
> index a5cd9d4..7dcd533 100644
> --- a/drivers/common/cnxk/roc_nix_irq.c
> +++ b/drivers/common/cnxk/roc_nix_irq.c
> @@ -202,9 +202,12 @@ nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)
> uint64_t reg;
>
> reg = plt_read64(nix->base + off);
> - if (reg & BIT_ULL(44))
> + if (reg & BIT_ULL(44)) {
> plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff),
> (uint8_t)(reg & 0xff));
> + /* Clear valid bit */
> + plt_write64(BIT_ULL(44), nix->base + off);
> + }
> }
>
> static void
> --
> 2.8.4
>
