> -----Original Message-----
> From: Ferruh Yigit <ferruh.yi...@intel.com>
> Sent: Wednesday, November 10, 2021 7:25 PM
> To: Apeksha Gupta <apeksha.gu...@nxp.com>;
> david.march...@redhat.com; andrew.rybche...@oktetlabs.ru
> Cc: dev@dpdk.org; Sachin Saxena <sachin.sax...@nxp.com>; Hemant
> Agrawal <hemant.agra...@nxp.com>
> Subject: [EXT] Re: [PATCH v9 3/5] net/enetfec: support queue configuration
>
> Caution: EXT Email
>
> On 11/10/2021 7:48 AM, Apeksha Gupta wrote:
> > This patch adds Rx/Tx queue configuration setup operations.
> > On packet reception the respective BD Ring status bit is set
> > which is then used for packet processing.
> >
> > Signed-off-by: Sachin Saxena <sachin.sax...@nxp.com>
> > Signed-off-by: Apeksha Gupta <apeksha.gu...@nxp.com>
>
> <...>
>
> > +
> > + rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_t[queue_idx]),
>
> Isn't 'fep->bd_addr_p_t[]' a 64-bit value?
>
> <...>
>
> > +
> > + rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_r[queue_idx]),
>
> Isn't 'fep->bd_addr_p_r[]' a 64-bit address, why doing endianness operation
> only on 32-bit and writing only 32-bit of it to register?
[Apeksha] As FEC supports 32bit address only and Tx/Rx descriptor addresses
should be within 32bit address range.
Our hardware expects 32 bit addresses and kernel UIO makes sure it provide
32bit address range.
