Moving struct rte_intr_handle as an internal structure to avoid any ABI breakages in future. Since this structure defines some static arrays and changing respective macros breaks the ABI. Eg: Currently RTE_MAX_RXTX_INTR_VEC_ID imposes a limit of maximum 512 MSI-X interrupts that can be defined for a PCI device, while PCI specification allows maximum 2048 MSI-X interrupts that can be used. If some PCI device requires more than 512 vectors, either change the RTE_MAX_RXTX_INTR_VEC_ID limit or dynamically allocate based on PCI device MSI-X size on probe time. Either way its an ABI breakage.
Discussion thread: https://mails.dpdk.org/archives/dev/2021-March/202959.html Change already included in 21.11 ABI improvement spreadsheet (item 42): https://docs.google.com/spreadsheets/d/1betlC000ua5SsSiJIcC54mCCCJnW6voH5Dqv9UxeyfE/edit#gid=0 Signed-off-by: Harman Kalra <hka...@marvell.com> --- doc/guides/rel_notes/deprecation.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index d9c0e65921..e95574b1ec 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -17,6 +17,9 @@ Deprecation Notices * eal: The function ``rte_eal_remote_launch`` will return new error codes after read or write error on the pipe, instead of calling ``rte_panic``. +* eal: Making ``struct rte_intr_handle`` internal to avoid any ABI breakages + in future. + * rte_atomicNN_xxx: These APIs do not take memory order parameter. This does not allow for writing optimized code for all the CPU architectures supported in DPDK. DPDK has adopted the atomic operations from -- 2.18.0
