On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszyn...@marvell.com> wrote:
>
> Add support for setting link mode.
>
> Signed-off-by: Tomasz Duszynski <tduszyn...@marvell.com>
> Signed-off-by: Jakub Palider <jpali...@marvell.com>
> ---
> drivers/common/cnxk/roc_bphy_cgx.c | 28 ++++++++++++
> drivers/common/cnxk/roc_bphy_cgx.h | 11 +++++
> drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++
> drivers/common/cnxk/version.map | 1 +
> 4 files changed, 101 insertions(+)
>
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
> b/drivers/common/cnxk/roc_bphy_cgx.c
> index dbdaddcd0..930057bb0 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.c
> +++ b/drivers/common/cnxk/roc_bphy_cgx.c
> @@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
> unsigned int lmac,
> return 0;
> }
>
> +int
> +roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
> + struct roc_bphy_cgx_link_mode *mode)
> +{
> + uint64_t scr1, scr0;
> +
> + if (roc_model_is_cn10k())
> + return -ENOTSUP;
> +
> + if (!roc_cgx)
> + return -EINVAL;
> +
> + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
> + return -EINVAL;
-ENODEV? Access the series, please attempt to have proper return value
if possible.
> +
> + if (!mode)
> + return -EINVAL;
> +
> + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
> + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
> + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX,
> mode->full_duplex) |
> + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
> + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
> + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE,
> BIT_ULL(mode->mode));
> +
> + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
> +}
> +
> int
> roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
> {
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
> b/drivers/common/cnxk/roc_bphy_cgx.h
> index a5e18565d..f68ddfcc9 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.h
> +++ b/drivers/common/cnxk/roc_bphy_cgx.h
> @@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
> __MAX_ROC_BPHY_CGX_ETH_LINK_MODE
> };
>
> +struct roc_bphy_cgx_link_mode {
> + bool full_duplex;
> + bool an;
> + unsigned int port;
> + enum roc_bphy_cgx_eth_link_speed speed;
> + enum roc_bphy_cgx_eth_link_mode mode;
> +};
> +
> struct roc_bphy_cgx_link_info {
> bool link_up;
> bool full_duplex;
> @@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx
> *roc_cgx);
> __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
> unsigned int lmac,
> struct roc_bphy_cgx_link_info *info);
> +__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
> + unsigned int lmac,
> + struct roc_bphy_cgx_link_mode *mode);
> __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
> unsigned int lmac);
> __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
> diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h
> b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> index 4e86ae4ea..ee7578423 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
> +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> @@ -5,10 +5,64 @@
> #ifndef _ROC_BPHY_CGX_PRIV_H_
> #define _ROC_BPHY_CGX_PRIV_H_
>
> +/* LINK speed types */
> +enum eth_link_speed {
> + ETH_LINK_NONE,
> + ETH_LINK_10M,
> + ETH_LINK_100M,
> + ETH_LINK_1G,
> + ETH_LINK_2HG, /* 2.5 Gbps */
> + ETH_LINK_5G,
> + ETH_LINK_10G,
> + ETH_LINK_20G,
> + ETH_LINK_25G,
> + ETH_LINK_40G,
> + ETH_LINK_50G,
> + ETH_LINK_80G,
> + ETH_LINK_100G,
> + ETH_LINK_MAX,
> +};
> +
> +/* Supported LINK MODE enums
> + * Each link mode is a bit mask of these
> + * enums which are represented as bits
> + */
> +enum eth_mode {
> + ETH_MODE_SGMII_BIT = 0,
> + ETH_MODE_1000_BASEX_BIT,
> + ETH_MODE_QSGMII_BIT,
> + ETH_MODE_10G_C2C_BIT,
> + ETH_MODE_10G_C2M_BIT,
> + ETH_MODE_10G_KR_BIT, /* = 5 */
> + ETH_MODE_20G_C2C_BIT,
> + ETH_MODE_25G_C2C_BIT,
> + ETH_MODE_25G_C2M_BIT,
> + ETH_MODE_25G_2_C2C_BIT,
> + ETH_MODE_25G_CR_BIT, /* = 10 */
> + ETH_MODE_25G_KR_BIT,
> + ETH_MODE_40G_C2C_BIT,
> + ETH_MODE_40G_C2M_BIT,
> + ETH_MODE_40G_CR4_BIT,
> + ETH_MODE_40G_KR4_BIT, /* = 15 */
> + ETH_MODE_40GAUI_C2C_BIT,
> + ETH_MODE_50G_C2C_BIT,
> + ETH_MODE_50G_C2M_BIT,
> + ETH_MODE_50G_4_C2C_BIT,
> + ETH_MODE_50G_CR_BIT, /* = 20 */
> + ETH_MODE_50G_KR_BIT,
> + ETH_MODE_80GAUI_C2C_BIT,
> + ETH_MODE_100G_C2C_BIT,
> + ETH_MODE_100G_C2M_BIT,
> + ETH_MODE_100G_CR4_BIT, /* = 25 */
> + ETH_MODE_100G_KR4_BIT,
> + ETH_MODE_MAX_BIT /* = 27 */
> +};
> +
> /* REQUEST ID types. Input to firmware */
> enum eth_cmd_id {
> ETH_CMD_GET_LINK_STS = 4,
> ETH_CMD_INTERNAL_LBK = 7,
> + ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
> ETH_CMD_INTF_SHUTDOWN = 12,
> ETH_CMD_SET_PTP_MODE = 34,
> };
> @@ -63,6 +117,13 @@ enum eth_cmd_own {
> /* struct eth_ctl_args */
> #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
>
> +/* struct eth_mode_change_args */
> +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22)
> +
> #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
>
> #endif /* _ROC_BPHY_CGX_PRIV_H_ */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index 205a0602b..15a6d3a3b 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -16,6 +16,7 @@ INTERNAL {
> roc_bphy_cgx_intlbk_enable;
> roc_bphy_cgx_ptp_rx_disable;
> roc_bphy_cgx_ptp_rx_enable;
> + roc_bphy_cgx_set_link_mode;
> roc_clk_freq_get;
> roc_error_msg_get;
> roc_idev_lmt_base_addr_get;
> --
> 2.25.1
>
