> -----Original Message----- > From: Chengwen Feng <fengcheng...@huawei.com> > Sent: Monday, May 24, 2021 9:23 PM > To: tho...@monjalon.net; ferruh.yi...@intel.com > Cc: dev@dpdk.org; jer...@marvell.com; Ruifeng Wang > <ruifeng.w...@arm.com>; vikto...@rehivetech.com; > bruce.richard...@intel.com; Honnappa Nagarahalli > <honnappa.nagaraha...@arm.com>; jerinjac...@gmail.com; > juraj.lin...@pantheon.tech; nd <n...@arm.com> > Subject: [PATCH v8 2/2] net/hns3: refactor SVE code compile method > > Currently, the SVE code is compiled only when -march supports SVE (e.g. '- > march=armv8.2a+sve'), there maybe some problem[1] with this approach. > > The solution: > a. If the minimum instruction set support SVE then compiles it. > b. Else if the compiler support SVE then compiles it. > c. Otherwise don't compile it. > > Note: this patch also fixes compile error with gcc8.3 + '-march=armv8.a+sve', > the error is arm_sve.h no such file or directory. > > [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html > > Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") > Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") > Cc: sta...@dpdk.org > > Signed-off-by: Chengwen Feng <fengcheng...@huawei.com> > --- > drivers/net/hns3/hns3_rxtx.c | 2 +- > drivers/net/hns3/meson.build | 20 +++++++++++++++++++- > 2 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c > index 1d7a769..9b2f082 100644 > --- a/drivers/net/hns3/hns3_rxtx.c > +++ b/drivers/net/hns3/hns3_rxtx.c > @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) > static bool > hns3_get_sve_support(void) > { > -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) > +#if defined(CC_SVE_ACLE_SUPPORT) > if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) > return false; > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) > diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build > index 53c7df7..aabcf23 100644 > --- a/drivers/net/hns3/meson.build > +++ b/drivers/net/hns3/meson.build > @@ -35,7 +35,25 @@ deps += ['hash'] > > if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') > sources += files('hns3_rxtx_vec.c') > - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' > + > + # compile SVE when: > + # a. support SVE in minimum instruction set baseline > + # b. it's not minimum instruction set, but compiler support > + if dpdk_conf.has('CC_SVE_ACLE_SUPPORT') > sources += files('hns3_rxtx_vec_sve.c') > + elif cc.has_argument('-march=armv8.2-a+sve') and > cc.check_header('arm_sve.h') > + cflags += ['-DCC_SVE_ACLE_SUPPORT=1'] > + sve_cflags = [] > + foreach flag: cflags > + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') > or > flag.startswith('-mtune=')) > + sve_cflags += flag > + endif > + endforeach > + hns3_sve_lib = static_library('hns3_sve_lib', > + 'hns3_rxtx_vec_sve.c', > + dependencies: [static_rte_ethdev], > + include_directories: includes, > + c_args: [sve_cflags, '-march=armv8.2-a+sve']) > + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') > endif > endif > -- > 2.8.1
Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
