From: Suanming Mou <suanmi...@nvidia.com>
This patch adds the struct defining UMR and RDMA write WQEs.
Signed-off-by: Suanming Mou <suanmi...@nvidia.com>
Signed-off-by: Matan Azrad <ma...@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 187 +++++++++++++++++++++------------
1 file changed, 121 insertions(+), 66 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c2cd2d9f70..1ffee5fd56 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -412,6 +412,127 @@ struct mlx5_cqe_ts {
uint8_t op_own;
};
+struct mlx5_wqe_rseg {
+ uint64_t raddr;
+ uint32_t rkey;
+ uint32_t reserved;
+} __rte_packed;
+
+#define MLX5_UMRC_IF_OFFSET 31u
+#define MLX5_UMRC_KO_OFFSET 16u
+#define MLX5_UMRC_TO_BS_OFFSET 0u
+
+struct mlx5_wqe_umr_cseg {
+ uint32_t if_cf_toe_cq_res;
+ uint32_t ko_to_bs;
+ uint64_t mkey_mask;
+ uint32_t rsvd1[8];
+} __rte_packed;
+
+struct mlx5_wqe_mkey_cseg {
+ uint32_t fr_res_af_sf;
+ uint32_t qpn_mkey;
+ uint32_t reserved2;
+ uint32_t flags_pd;
+ uint64_t start_addr;
+ uint64_t len;
+ uint32_t bsf_octword_size;
+ uint32_t reserved3[4];
+ uint32_t translations_octword_size;
+ uint32_t res4_lps;
+ uint32_t reserved;
+} __rte_packed;
+
+enum {
+ MLX5_BSF_SIZE_16B = 0x0,
+ MLX5_BSF_SIZE_32B = 0x1,
+ MLX5_BSF_SIZE_64B = 0x2,
+ MLX5_BSF_SIZE_128B = 0x3,
+};
+
+enum {
+ MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
+ MLX5_BSF_P_TYPE_CRYPTO = 0x1,
+};
+
+enum {
+ MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
+ MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
+ MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
+ MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
+};
+
+enum {
+ MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
+};
+
+enum {
+ MLX5_BLOCK_SIZE_512B = 0x1,
+ MLX5_BLOCK_SIZE_520B = 0x2,
+ MLX5_BLOCK_SIZE_4096B = 0x3,
+ MLX5_BLOCK_SIZE_4160B = 0x4,
+ MLX5_BLOCK_SIZE_1MB = 0x5,
+ MLX5_BLOCK_SIZE_4048B = 0x6,
+};
+
+#define MLX5_BSF_SIZE_OFFSET 30
+#define MLX5_BSF_P_TYPE_OFFSET 24
+#define MLX5_ENCRYPTION_ORDER_OFFSET 16
+#define MLX5_BLOCK_SIZE_OFFSET 24
+
+struct mlx5_wqe_umr_bsf_seg {
+ /*
+ * bs_bpt_eo_es contains:
+ * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
+ * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
+ * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
+ * es encryption_standard 4 bits at offset 0
+ */
+ uint32_t bs_bpt_eo_es;
+ uint32_t raw_data_size;
+ /*
+ * bsp_res contains:
+ * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
+ * res reserved 24 bits
+ */
+ uint32_t bsp_res;
+ uint32_t reserved0;
+ uint8_t xts_initial_tweak[16];
+ /*
+ * res_dp contains:
+ * res reserved 8 bits
+ * dp dek_pointer 24 bits at offset 0
+ */
+ uint32_t res_dp;
+ uint32_t reserved1;
+ uint64_t keytag;
+ uint32_t reserved2[4];
+} __rte_packed;
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+struct mlx5_umr_wqe {
+ struct mlx5_wqe_cseg ctr;
+ struct mlx5_wqe_umr_cseg ucseg;
+ struct mlx5_wqe_mkey_cseg mkc;
+ union {
+ struct mlx5_wqe_dseg kseg[0];
+ struct mlx5_wqe_umr_bsf_seg bsf[0];
+ };
+} __rte_packed;
+
+struct mlx5_rdma_write_wqe {
+ struct mlx5_wqe_cseg ctr;
+ struct mlx5_wqe_rseg rseg;
+ struct mlx5_wqe_dseg dseg[0];
+} __rte_packed;
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
/* GGA */
/* MMO metadata segment */
@@ -1096,72 +1217,6 @@ struct mlx5_ifc_create_mkey_in_bits {
u8 klm_pas_mtt[][0x20];
};
-enum {
- MLX5_BSF_SIZE_16B = 0x0,
- MLX5_BSF_SIZE_32B = 0x1,
- MLX5_BSF_SIZE_64B = 0x2,
- MLX5_BSF_SIZE_128B = 0x3,
-};
-
-enum {
- MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
- MLX5_BSF_P_TYPE_CRYPTO = 0x1,
-};
-
-enum {
- MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
- MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
- MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
- MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
-};
-
-enum {
- MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
-};
-
-enum {
- MLX5_BLOCK_SIZE_512B = 0x1,
- MLX5_BLOCK_SIZE_520B = 0x2,
- MLX5_BLOCK_SIZE_4096B = 0x3,
- MLX5_BLOCK_SIZE_4160B = 0x4,
- MLX5_BLOCK_SIZE_1MB = 0x5,
- MLX5_BLOCK_SIZE_4048B = 0x6,
-};
-
-#define MLX5_BSF_SIZE_OFFSET 30
-#define MLX5_BSF_P_TYPE_OFFSET 24
-#define MLX5_ENCRYPTION_ORDER_OFFSET 16
-#define MLX5_BLOCK_SIZE_OFFSET 24
-
-struct mlx5_wqe_umr_bsf_seg {
- /*
- * bs_bpt_eo_es contains:
- * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
- * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
- * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
- * es encryption_standard 4 bits at offset 0
- */
- uint32_t bs_bpt_eo_es;
- uint32_t raw_data_size;
- /*
- * bsp_res contains:
- * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
- * res reserved 24 bits
- */
- uint32_t bsp_res;
- uint32_t reserved0;
- uint8_t xts_initial_tweak[16];
- /*
- * res_dp contains:
- * res reserved 8 bits
- * dp dek_pointer 24 bits at offset 0
- */
- uint32_t res_dp;
- uint32_t reserved1;
- uint64_t keytag;
- uint32_t reserved2[4];
-} __rte_packed;
-
enum {
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
--
2.25.1
