From: Pavan Nikhilesh <pbhagavat...@marvell.com>
Add devargs to configure the platform specific getwork mode.
CN9K getwork mode by default is set to use dual workslot mode.
Add option to force single workslot mode.
Example:
--dev "0002:0e:00.0,single_ws=1"
CN10K supports multiple getwork prefetch modes, by default the
prefetch mode is set to none.
Add option to select getwork prefetch mode
Example:
--dev "0002:1e:00.0,gw_mode=1"
Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
Signed-off-by: Shijith Thotton <sthot...@marvell.com>
---
doc/guides/eventdevs/cnxk.rst | 18 ++++++++++++++++++
drivers/event/cnxk/cn10k_eventdev.c | 3 ++-
drivers/event/cnxk/cn9k_eventdev.c | 3 ++-
drivers/event/cnxk/cnxk_eventdev.c | 6 ++++++
drivers/event/cnxk/cnxk_eventdev.h | 6 ++++--
5 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst
index cf2156333..b2684d431 100644
--- a/doc/guides/eventdevs/cnxk.rst
+++ b/doc/guides/eventdevs/cnxk.rst
@@ -55,6 +55,24 @@ Runtime Config Options
-a 0002:0e:00.0,xae_cnt=16384
+- ``CN9K Getwork mode``
+
+ CN9K ``single_ws`` devargs parameter is introduced to select single workslot
+ mode in SSO and disable the default dual workslot mode.
+
+ For example::
+
+ -a 0002:0e:00.0,single_ws=1
+
+- ``CN10K Getwork mode``
+
+ CN10K supports multiple getwork prefetch modes, by default the prefetch
+ mode is set to none.
+
+ For example::
+
+ -a 0002:0e:00.0,gw_mode=1
+
- ``Event Group QoS support``
SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight
diff --git a/drivers/event/cnxk/cn10k_eventdev.c
b/drivers/event/cnxk/cn10k_eventdev.c
index 3cf07734b..310acc011 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -327,4 +327,5 @@ RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
- CNXK_SSO_GGRP_QOS "=<string>");
+ CNXK_SSO_GGRP_QOS "=<string>"
+ CN10K_SSO_GW_MODE "=<int>");
diff --git a/drivers/event/cnxk/cn9k_eventdev.c
b/drivers/event/cnxk/cn9k_eventdev.c
index 5be2776cc..44c7a0c3a 100644
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -395,4 +395,5 @@ RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);
RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);
RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=<int>"
- CNXK_SSO_GGRP_QOS "=<string>");
+ CNXK_SSO_GGRP_QOS "=<string>"
+ CN9K_SSO_SINGLE_WS "=1");
diff --git a/drivers/event/cnxk/cnxk_eventdev.c
b/drivers/event/cnxk/cnxk_eventdev.c
index 5f4075a31..0e2cc3681 100644
--- a/drivers/event/cnxk/cnxk_eventdev.c
+++ b/drivers/event/cnxk/cnxk_eventdev.c
@@ -406,6 +406,7 @@ static void
cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)
{
struct rte_kvargs *kvlist;
+ uint8_t single_ws = 0;
if (devargs == NULL)
return;
@@ -417,6 +418,11 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct
rte_devargs *devargs)
&dev->xae_cnt);
rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
dev);
+ rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value,
+ &single_ws);
+ rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value,
+ &dev->gw_mode);
+ dev->dual_ws = !single_ws;
rte_kvargs_free(kvlist);
}
diff --git a/drivers/event/cnxk/cnxk_eventdev.h
b/drivers/event/cnxk/cnxk_eventdev.h
index bf2c961aa..85f6058f2 100644
--- a/drivers/event/cnxk/cnxk_eventdev.h
+++ b/drivers/event/cnxk/cnxk_eventdev.h
@@ -14,8 +14,10 @@
#include "roc_api.h"
-#define CNXK_SSO_XAE_CNT "xae_cnt"
-#define CNXK_SSO_GGRP_QOS "qos"
+#define CNXK_SSO_XAE_CNT "xae_cnt"
+#define CNXK_SSO_GGRP_QOS "qos"
+#define CN9K_SSO_SINGLE_WS "single_ws"
+#define CN10K_SSO_GW_MODE "gw_mode"
#define NSEC2USEC(__ns) ((__ns) / 1E3)
#define USEC2NSEC(__us) ((__us)*1E3)
--
2.17.1
