From: Pavan Nikhilesh <pbhagavat...@marvell.com> Add meson build infra structure along with the event device SSO initialization and teardown functions.
Signed-off-by: Shijith Thotton <sthot...@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com> --- MAINTAINERS | 6 +++ doc/guides/eventdevs/cnxk.rst | 55 ++++++++++++++++++++++++ doc/guides/eventdevs/index.rst | 1 + drivers/event/cnxk/cnxk_eventdev.c | 68 ++++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 39 +++++++++++++++++ drivers/event/cnxk/meson.build | 13 ++++++ drivers/event/cnxk/version.map | 3 ++ drivers/event/meson.build | 1 + 8 files changed, 186 insertions(+) create mode 100644 doc/guides/eventdevs/cnxk.rst create mode 100644 drivers/event/cnxk/cnxk_eventdev.c create mode 100644 drivers/event/cnxk/cnxk_eventdev.h create mode 100644 drivers/event/cnxk/meson.build create mode 100644 drivers/event/cnxk/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 44f3d322e..d1ae33d48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1224,6 +1224,12 @@ M: Jerin Jacob <jer...@marvell.com> F: drivers/event/octeontx2/ F: doc/guides/eventdevs/octeontx2.rst +Marvell OCTEON CNXK +M: Pavan Nikhilesh <pbhagavat...@marvell.com> +M: Shijith Thotton <sthot...@marvell.com> +F: drivers/event/cnxk/ +F: doc/guides/eventdevs/cnxk.rst + NXP DPAA eventdev M: Hemant Agrawal <hemant.agra...@nxp.com> M: Nipun Gupta <nipun.gu...@nxp.com> diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst new file mode 100644 index 000000000..e94225bd3 --- /dev/null +++ b/doc/guides/eventdevs/cnxk.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell International Ltd. + +OCTEON CNXK SSO Eventdev Driver +========================== + +The SSO PMD (**librte_event_cnxk**) and provides poll mode +eventdev driver support for the inbuilt event device found in the +**Marvell OCTEON CNXK** SoC family. + +More information about OCTEON CNXK SoC can be found at `Marvell Official Website +<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_. + +Supported OCTEON CNXK SoCs +-------------------------- + +- CN9XX +- CN10XX + +Features +-------- + +Features of the OCTEON CNXK SSO PMD are: + +- 256 Event queues +- 26 (dual) and 52 (single) Event ports on CN10XX +- 52 Event ports on CN9XX +- HW event scheduler +- Supports 1M flows per event queue +- Flow based event pipelining +- Flow pinning support in flow based event pipelining +- Queue based event pipelining +- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow +- Event scheduling QoS based on event queue priority +- Open system with configurable amount of outstanding events limited only by + DRAM +- HW accelerated dequeue timeout support to enable power management + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/cnxk` for setup information. + +Debugging Options +----------------- + +.. _table_octeon_cnxk_event_debug_options: + +.. table:: OCTEON CNXK event device debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | SSO | --log-level='pmd\.event\.cnxk,8' | + +---+------------+-------------------------------------------------------+ diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst index 738788d9e..214302539 100644 --- a/doc/guides/eventdevs/index.rst +++ b/doc/guides/eventdevs/index.rst @@ -11,6 +11,7 @@ application through the eventdev API. :maxdepth: 2 :numbered: + cnxk dlb2 dpaa dpaa2 diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c new file mode 100644 index 000000000..b7f9c81bd --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#include "cnxk_eventdev.h" + +int +cnxk_sso_init(struct rte_eventdev *event_dev) +{ + const struct rte_memzone *mz = NULL; + struct rte_pci_device *pci_dev; + struct cnxk_sso_evdev *dev; + int rc; + + mz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t), + SOCKET_ID_ANY, 0); + if (mz == NULL) { + plt_err("Failed to create eventdev memzone"); + return -ENOMEM; + } + + dev = cnxk_sso_pmd_priv(event_dev); + pci_dev = container_of(event_dev->dev, struct rte_pci_device, device); + dev->sso.pci_dev = pci_dev; + + *(uint64_t *)mz->addr = (uint64_t)dev; + + /* Initialize the base cnxk_dev object */ + rc = roc_sso_dev_init(&dev->sso); + if (rc < 0) { + plt_err("Failed to initialize RoC SSO rc=%d", rc); + goto error; + } + + dev->is_timeout_deq = 0; + dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); + dev->max_num_events = -1; + dev->nb_event_queues = 0; + dev->nb_event_ports = 0; + + return 0; + +error: + rte_memzone_free(mz); + return rc; +} + +int +cnxk_sso_fini(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + /* For secondary processes, nothing to be done */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + roc_sso_rsrc_fini(&dev->sso); + roc_sso_dev_fini(&dev->sso); + + return 0; +} + +int +cnxk_sso_remove(struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini); +} diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h new file mode 100644 index 000000000..148b327a1 --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef __CNXK_EVENTDEV_H__ +#define __CNXK_EVENTDEV_H__ + +#include <rte_pci.h> + +#include <eventdev_pmd_pci.h> + +#include "roc_api.h" + +#define USEC2NSEC(__us) ((__us)*1E3) + +#define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" + +struct cnxk_sso_evdev { + struct roc_sso sso; + uint8_t is_timeout_deq; + uint8_t nb_event_queues; + uint8_t nb_event_ports; + uint32_t min_dequeue_timeout_ns; + uint32_t max_dequeue_timeout_ns; + int32_t max_num_events; +} __rte_cache_aligned; + +static inline struct cnxk_sso_evdev * +cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) +{ + return event_dev->data->dev_private; +} + +/* Common ops API. */ +int cnxk_sso_init(struct rte_eventdev *event_dev); +int cnxk_sso_fini(struct rte_eventdev *event_dev); +int cnxk_sso_remove(struct rte_pci_device *pci_dev); + +#endif /* __CNXK_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build new file mode 100644 index 000000000..e454dc863 --- /dev/null +++ b/drivers/event/cnxk/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell International Ltd. +# + +if not is_linux or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on 64-bit Linux' + subdir_done() +endif + +sources = files('cnxk_eventdev.c') + +deps += ['bus_pci', 'common_cnxk', 'net_cnxk'] diff --git a/drivers/event/cnxk/version.map b/drivers/event/cnxk/version.map new file mode 100644 index 000000000..ee80c5172 --- /dev/null +++ b/drivers/event/cnxk/version.map @@ -0,0 +1,3 @@ +INTERNAL { + local: *; +}; diff --git a/drivers/event/meson.build b/drivers/event/meson.build index 539c5aeb9..63d6b410b 100644 --- a/drivers/event/meson.build +++ b/drivers/event/meson.build @@ -6,6 +6,7 @@ if is_windows endif drivers = [ + 'cnxk', 'dlb2', 'dpaa', 'dpaa2', -- 2.17.1
