[dpdk-dev] [PATCH v2 4/5] net/hns3: check PCI config space writes

[Lijun Ou]

Here adds a check for the return value when calling
rte_pci_write_config.

Coverity issue: 363714
Fixes: cea37e513329 ("net/hns3: fix FLR reset")
Cc: sta...@dpdk.org

Signed-off-by: Lijun Ou <ouli...@huawei.com>
---
V1->V2:
- rte_pci_wirte_config -> rte_pci_write_config
---
 drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/net/hns3/hns3_ethdev_vf.c 
b/drivers/net/hns3/hns3_ethdev_vf.c
index 2e9bfda..2f6d91b 100644
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, 
bool op)
                ret = rte_pci_read_config(device, &control, sizeof(control),
                                    (pos + PCI_MSIX_FLAGS));
                if (ret < 0) {
-                       PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
+                       PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x",
                                     (pos + PCI_MSIX_FLAGS));
                        return -ENXIO;
                }
@@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device *device, 
bool op)
                        control |= PCI_MSIX_FLAGS_ENABLE;
                else
                        control &= ~PCI_MSIX_FLAGS_ENABLE;
-               rte_pci_write_config(device, &control, sizeof(control),
-                                    (pos + PCI_MSIX_FLAGS));
+               ret = rte_pci_write_config(device, &control, sizeof(control),
+                                         (pos + PCI_MSIX_FLAGS));
+               if (ret < 0) {
+                       PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
+                                   (pos + PCI_MSIX_FLAGS));
+               }
                return 0;
        }
        return -ENXIO;
-- 
2.7.4