> -----Original Message-----
> From: McDaniel, Timothy <timothy.mcdan...@intel.com>
> Sent: Saturday, October 17, 2020 1:21 PM
> Cc: dev@dpdk.org; Carrillo, Erik G <erik.g.carri...@intel.com>; Eads, Gage
> <gage.e...@intel.com>; Van Haaren, Harry <harry.van.haa...@intel.com>;
> jer...@marvell.com
> Subject: [PATCH v2 12/22] event/dlb2: add port link
>
> Add port link entry point. Directed queues are identified and created
> at this stage. Their setup deferred until link-time, at which
> point we know the directed port ID. Directed queue setup
> will only fail if this queue is already setup or there are
> no directed queues left to configure.
>
> Signed-off-by: Timothy McDaniel <timothy.mcdan...@intel.com>
> ---
> drivers/event/dlb2/dlb2.c | 308 +++++++++++++-
> drivers/event/dlb2/dlb2_iface.c | 6 +
> drivers/event/dlb2/dlb2_iface.h | 6 +
> drivers/event/dlb2/pf/base/dlb2_resource.c | 633
> +++++++++++++++++++++++++++++
> drivers/event/dlb2/pf/dlb2_main.c | 10 +
> drivers/event/dlb2/pf/dlb2_pf.c | 50 +++
> 6 files changed, 1009 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
> index e956a7a..b448f59 100644
> --- a/drivers/event/dlb2/dlb2.c
> +++ b/drivers/event/dlb2/dlb2.c
> @@ -828,9 +828,8 @@ dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2,
> sched_type = RTE_SCHED_TYPE_ORDERED;
> else
> sched_type = RTE_SCHED_TYPE_PARALLEL;
> - } else {
> + } else
> sched_type = evq_conf->schedule_type;
> - }
>
> cfg.num_atomic_inflights =
> DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE;
> cfg.num_sequence_numbers = evq_conf-
> >nb_atomic_order_sequences;
> @@ -866,9 +865,8 @@ dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2,
> if (ev_queue->depth_threshold == 0) {
> cfg.depth_threshold =
> RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
> ev_queue->depth_threshold =
> RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
> - } else {
> + } else
> cfg.depth_threshold = ev_queue->depth_threshold;
> - }
These two changes should be in patch 10 ("event/dlb2: add queue setup").
Besides that:
Reviewed-by: Gage Eads <gage.e...@intel.com>
Thanks,
Gage
