On Mon, Jul 06, 2015 at 04:51:33PM +0800, Zhigang Lu wrote: > On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware > buffer manager require a 128-byte alignment. With this change, we > allow configuration based override of the element alignment, and > default to RTE_CACHE_LINE_SIZE if left unspecified. > > Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7 > Signed-off-by: Zhigang Lu <zlu at ezchip.com>
This looks an OK change. However, would it be worthwhile making this a runtime parameter rather than a compile-time one? Is it likely that we will ever have a case where someone wants two mempools with different alignments (and where using the larger of the two would be problematic)? /Bruce
